Digital Clock Synchronization Using PLL Reset and Masking
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Solution Overview
Problem
Existing Automated Test Equipment (ATE) systems face challenges in synchronizing digital clocks across multiple channels, particularly for close clock frequencies, leading to inefficiencies and increased costs due to the need for cumbersome synchronization methods and resource-intensive infrastructure.
Innovation Solution
A centralized reference clock and synchronization signal are distributed to channel cards, where a local clock multiplier, Phase Locked Loop (PLL), and dividers are used to achieve repeatable phase synchronization, eliminating the need for a super-period clock and minimizing central resources, with a settling time of microseconds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a super-period clock is used for synchronization, then phase synchronization can be achieved, but the infrastructure becomes more resource-intensive and complex
Solution Approach 1:
The patent extracts the synchronization function from the complex super-period clock infrastructure and implements it through a simplified mechanism using a synchronization signal that resets the clock multiplier counter. This removes the need for elaborate synchronization infrastructure while maintaining reliable phase alignment across channels.
Solution Approach 2:
The patent introduces a synchronization signal as an intermediary element that mediates between the central clock source and local clock multipliers. This signal coordinates the resetting of counters across different channels, achieving phase synchronization without requiring complex inter-channel infrastructure.
2Reliability
If centralized synchronization methods are used, then phase alignment can be achieved, but the settling time increases and productivity decreases
Solution Approach 1:
The patent applies preliminary action by pre-configuring the clock multiplier with a counter that is rapidly reset by the synchronization signal. This allows the system to quickly establish phase alignment at the start of each test cycle, minimizing settling time and maximizing productivity.
Solution Approach 2:
The patent implements dynamic synchronization where the counter reset timing is adaptively controlled by the synchronization signal. This dynamic approach allows the system to achieve synchronization in microseconds rather than requiring extended settling periods, thereby improving test execution speed.
3Adaptability or versatility
If local clock multiplication is implemented, then channel-specific frequencies can be generated, but phase consistency across channels becomes difficult to maintain
Solution Approach 1:
The patent implements feedback through the synchronization signal that monitors and coordinates the phase state of local clock multipliers. By resetting the counter based on this feedback signal, the system maintains consistent phase relationships across channels while allowing each channel to operate at its required frequency.
Solution Approach 2:
The patent segments the clock generation function into independent local clock multipliers for each channel, each capable of generating channel-specific frequencies. The phase consistency is maintained through coordinated counter resetting rather than through a unified central clock distribution, allowing frequency adaptability while preserving phase relationships.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable and cost-effective synchronization of digital clocks across channels, ensuring repeatable phase alignment even for close clock frequencies, reducing test time and infrastructure requirements.
Implementation Method 1
A clock multiplier provided locally on the channel card for multiplying the reference frequency by a predetermined integer or N-fractional ratio is reset locally on the channel card in response to the distributed synchronizing signal
Data Source
AI summary
The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said digital clocks from said reference clock using a clock multiplier, respectively, resetting said clock multiplier in response to said synchronizing signal, and masking an output signal of said clock multiplier during settling time of said clock multiplier.