Digital Compute Hardware for Neural Network Scaling and Aggregation
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Solution Overview
Problem
Current digital-compute hardware lacks an efficient pipelined implementation of digital scaling, offset, and aggregation operations that support element-by-element programmable scale and offset factors, which is crucial for optimizing neural network operations in Analog-AI systems.
Innovation Solution
A method involving time-multiplexed parallel pipelining of digital data words through a datapath that includes storing data in dedicated slope and offset memories, performing fused-multiply-add operations, and allowing simultaneous reading and writing for energy-efficient access, enabling efficient vectorized-scaling, aggregation, and rectified-linear operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional microprocessor or multi-processor solutions are used for digital scaling, offset, and aggregation operations, then general-purpose computing flexibility is achieved, but energy efficiency significantly deteriorates
Solution Approach 1:
The patent segments the computing architecture into specialized functional units: separate slope memory and offset memory structures, dedicated fused-multiply-add units, and distinct pipelined datapaths for scaling and aggregation operations. This segmentation allows each component to be optimized for its specific function, achieving high energy efficiency while maintaining manageable complexity through modular design.
Solution Approach 2:
The patent implements universal datapaths that can handle multiple operations (scaling, offset, aggregation) through configurable hardware components. The fused-multiply-add units and memory structures serve multiple purposes within the neural network processing pipeline, reducing overall system complexity while maintaining versatility for different computing tasks.
2Productivity
If digital scaling, offset, and aggregation operations are implemented without pipelining, then hardware simplicity is maintained, but processing speed and productivity deteriorate
Solution Approach 1:
The patent implements preliminary action through separate slope memory and offset memory structures that pre-store scaling parameters, and through pipelined datapaths that prepare data for subsequent operations. This allows scaling and aggregation operations to proceed in parallel stages, significantly improving processing throughput while keeping each individual stage relatively simple.
3Adaptability or versatility
If element-by-element programmable scale and offset factors are implemented, then adaptability for neural network operations is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by providing element-by-element programmable scale and offset factors that can be independently configured for different neural network operations. Each element in the data vector can have its own scaling parameters stored in dedicated memory structures, allowing fine-grained adaptability while maintaining a regular, predictable hardware architecture that limits overall complexity.
Data Source
AI summary
An efficient pipelined implementation of digital scaling, offset and aggregation operation supports element-by-element programmable scale and offset factors. The method includes time-multiplexed parallel pipelining of a plurality of digital data words, each of the plurality of digital data words encoding an N-bit signed integer, from one of a plurality of receive-registers through a datapath that can either (1) store the plurality of digital data words directly in a dedicated first memory, (2) store the plurality of digital data words directly in a dedicated second memory, or (3) direct the plurality of digital data words into a parallel set of fused-multiply-add units. The method further includes multiplying each digital data word by a corresponding data-word retrieved from the dedicated first memory to form product data words and adding the product data words to a corresponding data-word retrieved from the dedicated second memory to form an output sum-and-product data words.