Digital Correlated Double Sampling Using Successive Approximation ADC

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Solution Overview

Problem

Conventional correlated double sampling techniques in CMOS imagers suffer from slow conversion speeds and noise issues, particularly in high-resolution applications, which limit their ability to achieve high frame rates required for video output.

Innovation Solution

Implementing a digital correlated double sampling architecture that performs successive approximation analog-to-digital conversions of pixel reset and image signals in the digital domain, using a most significant bit (MSB)-first format, allowing for subtraction of digital pixel reset signals from digital pixel image signals within one row time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If single-slope analog-to-digital converters are used in column parallel pixel array readout architecture, then reliable monotonicity and relatively simple circuits are achieved, but conversion speed becomes too slow for high frame rate video output

Engineering Contradiction:

Improvemonotonicity reliabilityVSAvoidconversion speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent divides the conversion process into two separate stages: first converting the reset signal to digital, then converting the image signal to digital. This segmentation allows each converter to operate independently and completes both conversions within the same row time, achieving high conversion speed while maintaining reliability through the use of proven single-slope converter design in each stage

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs the reset signal conversion before the image signal conversion, and completes both conversions within one row time. This preliminary action of converting the reset signal first allows the system to prepare the digital reference value in advance, enabling fast correlated double sampling without exceeding the row time constraint

Inventive Principle:

Principle #10Preliminary action

2Measurement precision

If digital correlated double sampling is implemented, then noise reduction and offset correction are improved, but conversion time increases when using slow analog-to-digital converters

Engineering Contradiction:

Improvenoise reduction capabilityVSAvoidtotal conversion time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent changes the conversion rate parameter by using two parallel single-slope analog-to-digital converters operating simultaneously on different signals (reset and image). This parameter change allows both conversions to complete within one row time, reducing total conversion time while maintaining the noise reduction benefits of digital correlated double sampling

Inventive Principle:

Principle #35Parameter changes

3Measurement precision

If high resolution (12-14 bits) is achieved for image enhancement operations, then tone reproduction and gamma correction are improved, but conversion time increases significantly

Engineering Contradiction:

Improveimage resolutionVSAvoidframe rate

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent maintains continuous useful action by performing both analog-to-digital conversions (reset signal and image signal) within the same row time period. This continuous operation ensures that high-resolution conversion (12-14 bits) is completed without interrupting the video frame rate, achieving both high image quality and high productivity

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS7876371B2Systems and methods to perform digital correlated double sampling using successive approximation analog to digital conversion techniques

Publication Date: 2011.01.25 APTINA IMAGING CORP

AI summary

An imager includes a successive approximation analog-to-digital converter (SA-ADC) and an arithmetic memory. The successive approximation analog-to-digital converter converts analog representations of pixel reset and image signals for a pixel to digital representations of the pixel reset and image signals. The arithmetic memory generates a difference signal that represents the difference between the digital representations of the pixel reset signal and the pixel image signal using a most-significant-bit-first (MSB-first) calculation.