Digital Counter Timing Control for Ultrasonic Pulse Width
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Solution Overview
Problem
High-frequency ultrasonic transducers require higher effective sampling rates to accurately measure thin test pieces, but existing methods using phase lock loops or delay components introduce noise and delay errors, increasing costs and power consumption.
Innovation Solution
A digital counter sets the coarse delay and width of the high voltage excitation pulse, which is then fine-tuned by an RC time constant circuit, allowing for precise adjustment of the pulse delay and width, enabling higher sampling rates through interleaving without the noise and jitter issues of phase lock loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If phase lock loops or delay components are used to fine delay the sample clock signal, then the digital sampling rate can be increased through interleaving, but noise levels and clock jitter increase causing delay errors and sampling rate errors
Solution Approach 1:
The patent replaces the mechanical/electrical phase lock loop system with a digital counter-based timing control system. The digital counter increments on each excitation pulse and generates gate signals at precise digital clock edges, eliminating the need for analog phase lock loops and delay components that introduce noise and jitter.
Solution Approach 2:
The patent changes the timing control parameter from analog phase/delay adjustments to digital count values. By incrementing the digital counter and using its output to generate gate signals synchronized to digital clock edges, the system achieves fine timing control without the noise and jitter inherent in analog delay components.
2Measurement precision
If high frequency ultrasonic transducers are used to inspect thin test pieces, then measurement capability for thin pieces is improved, but the required sampling rate increases leading to higher cost and power consumption
Solution Approach 1:
The patent segments the sampling process into multiple interleaved sequences, each sampled at a lower rate. By using the digital counter to generate multiple gate signals that stagger the sampling of different phases of the ultrasonic echo, the system achieves an effective high sampling rate equivalent to 250 MHz or greater while using individual ADCs operating at lower rates, reducing power consumption and cost.
3Productivity
If the time interval for phase shifting the excitation pulse is made finer than the digital sampling interval, then interleaving can be implemented to achieve higher effective sampling rate, but the device complexity increases
Solution Approach 1:
The patent makes the digital counter serve multiple functions: it counts excitation pulses, generates precise timing gates for interleaved sampling, and provides phase shifting control. This single digital component replaces what would otherwise require separate phase lock loops, delay components, and sampling control circuits, reducing overall device complexity while achieving high effective sampling rates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for effective digital sampling of high-frequency return echoes from ultrasonic transducers, achieving higher sampling rates while reducing noise and power consumption, thus supporting accurate thickness measurements and flaw detection in thin test pieces.
Implementation Method 1
which is then sent to a fine delay analog circuit such as a resistor-capacitor (RC) time constant for fine tuning the coarse delay
Data Source
AI summary
A pulse generation circuit and method includes using digital signals to trigger a first and second varying analog signals and detecting when they reach one or more reference levels. In response to the first and second varying analog signals reaching one or more reference levels, a first and a second digital control signals are produced and provided as input to a pulser producing a voltage excitation pulse having a width and timing defined by the first and second digital control signals.