Digital Data Recovery Circuit for Precise Jitter Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current Clock and Data Recovery (CDR) circuits face limitations in detecting jitter due to sensitivity to process variations and power supply voltage changes, affecting the precision of signal transmission between chips and circuit blocks, which hinders the improvement of system performance.
Innovation Solution
A data recovery circuit comprising an analog-digital converter, phase detector, phase estimator, and data determining circuit that calculates the position of crossing points and adjusts the phase of the clock signal digitally, reducing reliance on analog components and stabilizing performance against process and voltage variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an analog Phase Interpolator (PI) is used to change the phase of a clock signal in the CDR circuit, then the phase adjustment capability is achieved, but the circuit becomes sensitive to process variations and power supply voltage changes, reducing reliability
Solution Approach 1:
The patent replaces the analog Phase Interpolator (PI) circuit with a digital phase adjustment mechanism. Instead of using analog components to adjust clock phase, the invention uses digital logic circuits that operate on sampled data sequences. This substitution eliminates the sensitivity to process variations and power supply voltage changes that plagues analog PI circuits, while maintaining the necessary phase adjustment capability through digital processing of the data sequences.
Solution Approach 2:
The patent creates a digital representation (copy) of the phase information through the sequence of digital codes generated by the analog-digital converter. Rather than directly manipulating the analog clock signal phase with sensitive analog components, the system captures phase information in the temporal pattern of digital codes and processes this digital copy through logic circuits to achieve phase adjustment without analog sensitivity issues.
2Measurement precision
If the phase resolution of the internal clock signal is increased to improve jitter detection precision, then the detection sensitivity is improved, but the device complexity increases due to the need for higher precision phase adjustment mechanisms
Solution Approach 1:
The patent replaces complex high-precision analog phase adjustment mechanisms with simpler digital logic circuits. By converting the phase adjustment function into the digital domain, the system achieves high jitter detection precision through digital processing of code sequences rather than through complex analog phase interpolation with fine resolution control, thereby reducing device complexity while maintaining or improving measurement precision.
Solution Approach 2:
The patent transitions the phase adjustment problem from the analog time domain to the digital code sequence domain. Instead of adjusting phase continuously in time with high-resolution analog controls, the system represents phase information in the discrete temporal dimension of digital code transitions, enabling precise jitter detection through digital logic operations on the sequence of codes rather than through complex analog phase control mechanisms.
Data Source
AI summary
A data recovery circuit includes an analog-digital converter creating a digital code sequence, a phase detector calculating a position of a crossing point from the digital code sequence, a phase estimator acquiring a presumed position of a data center point of a data sequence based on the position of the crossing point, and a data determining circuit extracting the sequence of data determination values from the digital code sequence based on the position of the crossing point and the presumed position of the data center point.