Digital Dead-Time Control for Zero-Voltage Switching

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Solution Overview

Problem

Inductor-based switching converters face efficiency loss and electrical stress due to large voltage swings and pulsed currents at the switch node, which are challenging to address with analog circuitry, especially in advanced CMOS processes.

Innovation Solution

A digital, standard cell-based technique for soft-switching that uses a digital delay line to sense the maximum inductor current and adjust the dead-time between switch transitions, ensuring optimal discharge of parasitic capacitance and reducing current and voltage stress, implemented without fuses or calibration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If analog circuitry is used for soft-switching, then zero-voltage switching can be achieved, but the circuit becomes challenging to scale and calibrate in sub-micron manufacturing processes

Engineering Contradiction:
Improvezero-voltage switching performanceVSAvoidanalog circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces analog circuitry with digital circuitry for implementing soft-switching control. Specifically, it uses a digital delay line with programmable delay elements to control the dead-time between switch transitions, substituting complex analog components (sense resistors, current mirrors, amplifiers, comparators) with digital logic elements that are more scalable and easier to calibrate in sub-micron CMOS processes

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the control parameter from analog voltage/current signals to digital delay time. By programmatically adjusting the delay value in the digital delay line, the system can optimize dead-time for different operating conditions without requiring physical component changes or complex analog calibration circuits

Inventive Principle:
Principle #35Parameter changes

2Stress or pressure

If dead-time is increased to allow parasitic capacitance discharge, then voltage stress on switches is reduced, but switching frequency and efficiency are degraded

Engineering Contradiction:
Improvevoltage stress on switchesVSAvoidswitching frequency
Core Design Contradiction:
Stress or pressureVSProductivity

Solution Approach 1:

The patent implements dynamic dead-time adjustment by using a digital delay line whose delay value can be programmatically changed based on operating conditions. This allows the dead-time to be optimized in real-time for different load conditions, voltage levels, and temperature ranges, rather than using a fixed dead-time value, thereby maintaining both low voltage stress and high switching frequency

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If inductor current is sensed and used to adjust dead-time, then zero-voltage switching accuracy is improved, but measurement and control complexity increases

Engineering Contradiction:
Improveinductor current measurement accuracyVSAvoidsensing and control circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces complex analog sensing circuitry with digital current sensing methods. It uses a digital delay line where the delay value is determined based on inductor current information, and this digital representation is then used to programmatically adjust the dead-time. This substitution of analog sensing with digital measurement and control simplifies the overall system while maintaining or improving measurement accuracy

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10069397B2Digitally controlled zero voltage switching
Publication Date: 2018.09.04 INTEL CORP
  • US10069397B2 patent drawing
  • US10069397B2 patent drawing
  • US10069397B2 patent drawing

AI summary

Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry. The switch controller circuitry includes dead time logic circuitry to determine an estimated dead time interval between a turn off of a first switch and a turn on of a second switch. The first switch and the second switch are coupled at a switched node. The estimated dead time interval is determined based, at least in part, on a difference between an input voltage, Vin, and a switched voltage, Vsw, detected at the switched node just prior to turning off the first switch, a parasitic capacitance, Cpar, associated with the switched node and a maximum inductor current, IL,max. The difference between Vin and Vsw represents the maximum inductor current.