Digital Dejitter Circuit for Telecom Clock Smoothing
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Solution Overview
Problem
In telecom circuits, asynchronous mapping of low-speed tributaries to high-speed Sonet/SDH signals results in frequency differences between reference clocks, leading to stuffing and destuffing bits, payload pointer issues, and low-frequency wander, causing gapped and jittery demapped clocks, which existing systems address using expensive analog elements.
Innovation Solution
A digital logic circuit that includes a gapped clock smoother, frequency comparator, digital filter, and phase correction unit to convert the gapped and jittery clock into a smoothed clock with low jitter, matching the frequency of the input clock, using digital components that can be reused and re-mapped in FPGA or ASICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog elements are used to smooth gapped and jittery clocks, then clock quality is improved, but cost and manufacturing complexity increase
Solution Approach 1:
The patent replaces analog electronic circuits with a fully digital logic implementation. The digital dejitter circuit uses digital counters, comparators, and logic gates to achieve clock smoothing and jitter attenuation, eliminating the need for analog components while maintaining clock quality and reducing manufacturing cost and process dependency
Solution Approach 2:
The patent changes the operational parameters by using digital counting and comparison mechanisms instead of analog filtering. The digital circuit measures time intervals between clock edges using counters and compares them against reference values, dynamically adjusting the output clock phase and frequency to achieve jitter attenuation without analog elements
2Reliability
If analog elements are used to smooth gapped and jittery clocks, then clock quality is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex analog filtering circuits with a structured digital logic implementation. The digital circuit uses synchronized counters, comparators, and control logic that can be systematically designed and verified, reducing overall circuit complexity while achieving the same clock smoothing function
Solution Approach 2:
The patent divides the dejitter function into distinct digital modules: a counter module for measuring time intervals, a comparator module for evaluating frequency differences, and a control module for generating phase correction signals. This segmentation makes the circuit easier to design, verify, and manufacture compared to monolithic analog circuits
3Ease of manufacture
If digital logic is used to convert gapped clock to smoothed clock, then manufacturing cost is reduced, but achieving low jitter requires complex digital processing
Solution Approach 1:
The patent uses straightforward digital logic operations (counting, comparing, and conditional signal generation) to achieve jitter attenuation. The digital circuit measures time intervals using counters, compares measured intervals against reference values using comparators, and generates correction signals based on simple logical conditions, avoiding complex digital processing while maintaining low manufacturing cost
Data Source
AI summary
Digital logic receives a gapped and jittery clock signal with specified frequency and frequency offset allowed by specification and a reference clock signal with same specified frequency and different frequency offset allowed by specification having low jitter. The digital logic adds and/or removes cycles from the reference clock signal over an extended period of time to produce a produced clock signal with low jitter that has a frequency that approaches the frequency of the gapped and jittery clock signal. The produced clock signal being provided as feedback to the digital frequency comparator and also acts as final dejitter smooth clock output with 50% duty cycle.