Digital Delay Buffer With Segmented Memory For SONET Latency
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Solution Overview
Problem
Existing techniques for controlling latency delays in data streams across synchronous optical networks (SONET) introduce substantial latency, making it difficult to align data streams efficiently without incurring processing delays, especially when data portions experience unexpectedly long delays.
Innovation Solution
A digital data stream delay buffer system comprising a fast processing, small capacity (FPSC) memory section and a slow processing, large capacity (SPLC) memory section, where the control section determines whether to use the SPLC section based on detected delays to generate an aligned data stream, minimizing latency delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SPLC memory is used to control latency delays, then data capacity is sufficient, but processing speed decreases and latency increases
Solution Approach 1:
The delay buffer is segmented into two distinct memory sections: an FPSC memory section for fast processing of routine data and an SPLC memory section for handling delayed data portions. This segmentation allows the system to process most data quickly while having dedicated resources for managing latency delays, thus resolving the contradiction between data capacity and processing speed.
2Productivity
If larger block sizes are used in SPLC memory, then throughput improves, but latency delays increase
Solution Approach 1:
The system dynamically adjusts its operation mode based on detected delay values. When delays are within acceptable ranges, the FPSC memory processes data with low latency. When delays exceed thresholds, the system dynamically switches to using the SPLC memory section, optimizing throughput for delayed portions without permanently increasing latency for all data.
3Reliability
If existing latency control techniques are used, then delay compensation is achieved, but substantial processing latency is introduced
Solution Approach 1:
The FPSC memory section acts as an intermediary between the incoming data stream and the final aligned output. It provides a fast path for processing most data portions without substantial latency, while the SPLC memory section serves as a mediator for handling exceptional delayed portions, thus achieving delay compensation without introducing substantial processing latency for routine data.
Data Source
AI summary
A digital delay buffer may be provided with both a fast processing, small capacity memory section and a slow processing, large capacity memory section. The use of two memory sections allows the buffer to generate an aligned data stream with n-bit block level latencies from a plurality of delayed data portions, even if one of the portions is subjected to an undue delay.