Digital Delay Circuit for Matched Clock Edge Control
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Solution Overview
Problem
Conventional delay control circuits for introducing arbitrary delays into clock signals face challenges in achieving high accuracy while minimizing circuit area and power consumption, often requiring large circuit areas and high power consumption, especially when implementing analog circuits.
Innovation Solution
A delay control circuit comprising a first and second variable delay circuit, a control circuit, and a generation circuit, where the control circuit ensures identical delays on both edges of the input signal, allowing for accurate edge delay adjustment and reducing duty ratio variation, thereby achieving high accuracy without the need for analog circuits and external components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog PLL or DLL circuits are used for high accuracy delay control, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The delay control circuit is divided into multiple digital delay elements arranged in series, each contributing a discrete delay amount. By segmenting the total delay into multiple smaller digital stages, the circuit achieves high precision delay control without requiring complex analog components, thus reducing circuit area while maintaining accuracy.
Solution Approach 2:
The patent replaces analog delay control mechanisms (PLL/DLL circuits) with a digital delay control system. This substitution eliminates the need for analog components such as voltage-controlled oscillators and phase detectors, significantly reducing circuit complexity and power consumption while maintaining high delay control accuracy through digital counting and control logic.
2Measurement precision
If analog PLL or DLL circuits are used for high accuracy delay control, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent replaces power-hungry analog PLL/DLL circuits with a digital delay control system consisting of programmable delay elements and digital counters. This substitution dramatically reduces power consumption by eliminating analog signal processing while maintaining high delay precision through digital control mechanisms that consume minimal power.
Solution Approach 2:
The delay control is achieved through periodic clock signals and counter-based control logic rather than continuous analog signal processing. The digital system updates delay settings at discrete intervals synchronized with the clock period, reducing average power consumption compared to continuously operating analog circuits while maintaining accurate delay control.
3Device complexity
If buffer is used for arbitrary delay, then device complexity is reduced, but measurement precision deteriorates
Solution Approach 1:
Instead of using a single buffer stage, the patent divides the delay path into multiple segmented delay elements, each controlled by independent digital control signals. This segmentation allows precise control of the total delay by adjusting individual segment delays, achieving high measurement precision while keeping each segment simple and the overall circuit area compact.
Solution Approach 2:
The patent implements dynamically controllable delay elements where the delay amount of each segment can be adjusted in real-time through digital control signals. This dynamic control capability enables precise arbitrary delay settings without requiring complex fixed-delay buffer structures, achieving high precision with simplified circuitry.
Data Source
AI summary
A first variable delay circuit delays an input signal, introduces a first delay into a first edge of the input signal, and generates a first delay signal. A second variable delay circuit delays the input signal, introduces a second delay into a second edge, and generates a second delay signal. A control circuit controls the first variable delay circuit and the second variable delay circuit such that the first delay and the second delay are identical. A generation circuit combines the first edge of the first delay signal and the second edge of the second delay signal, and generates a third delay signal.