Digitally Controlled Delay Line with Single-Sided Tunable Cells
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Solution Overview
Problem
Existing digitally controlled delay lines (DCDLs) face challenges in achieving linear delay time control due to variations in transistor switching speeds, leading to reduced precision and increased complexity in implementing programmable delay times for both rising and falling signal transitions.
Innovation Solution
The implementation of single-sided tunable delay cells within DCDL circuits, which receive signals of the same polarity, reduces circuit size and complexity by using fewer transistors and minimizing process variation effects, thereby enhancing delay time linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional DCDL circuits use separate delay cells for both rising and falling signal transitions, then comprehensive delay control is achieved, but circuit size and complexity increase
Solution Approach 1:
The delay cell is designed to handle both rising and falling signal transitions using the same circuit structure. The single delay cell configuration processes both transition types by controlling the switching of transistors based on the input signal polarity, eliminating the need for separate delay cells for each transition type while maintaining comprehensive delay control capability
Solution Approach 2:
The patent combines the functionality of separate rising-edge and falling-edge delay cells into a single unified delay cell structure. By merging these functions, the circuit achieves the same delay control for both transition types with reduced component count, directly addressing the contradiction between versatility and complexity
2Ease of manufacture
If DCDL circuits use conventional delay cells, then implementation is straightforward, but delay time linearity deteriorates due to transistor switching speed variations
Solution Approach 1:
The patent introduces可调 capacitance elements that can be controlled to compensate for variations in transistor switching speeds. By dynamically adjusting the capacitance parameters in response to detected delay errors, the system maintains linear delay time control across different operating conditions and transistor variations, thereby improving manufacturing precision without complicating the implementation
3Measurement precision
If DCDL circuits implement programmable delay times for both rising and falling transitions with full compensation, then delay precision improves, but circuit complexity increases
Solution Approach 1:
The same delay cell structure and control mechanism are used for both rising and falling transitions. The control circuit detects delay errors and adjusts the capacitance elements to compensate for variations, achieving precise delay control for both transition types without requiring separate compensation circuits, thus maintaining delay precision while limiting complexity increase
Data Source
AI summary
A digitally controlled delay line (DCDL) includes an input terminal, an output terminal, and a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal. Each stage of the plurality of stages includes first and second inverters configured to selectively propagate the signal along the first signal path, third and fourth inverters configured to selectively propagate the signal along the second signal path, and a fifth inverter configured to selectively propagate the signal from the first signal path to the second signal path.