Digitally Controlled Delay Line With Single-Sided Tunable Stages
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Solution Overview
Problem
Existing digitally controlled delay lines (DCDLs) face challenges in achieving linear delay time control due to variations in transistor switching speeds, particularly when handling signals with both rising and falling transitions, leading to increased circuit size and complexity.
Innovation Solution
The implementation of single-sided tunable delay cells within DCDLs, configured to receive signals of the same polarity, reduces circuit complexity and process variation effects by using fewer transistors and optimizing delay time control based on same-type transistor switching speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If DCDL circuits use traditional delay stages to handle both rising and falling signal transitions, then the circuit can process complete signal waves, but the circuit size and complexity increase due to requiring more transistors
Solution Approach 1:
The delay line is segmented into multiple delay stages, where each stage is further divided into first and second delay paths handling rising and falling transitions separately. This segmentation allows independent optimization of each path, reducing the transistor count per stage while maintaining overall signal processing capability.
Solution Approach 2:
Different delay stages are configured with different numbers of delay elements based on local signal transition requirements. The first delay path uses a first number of delay elements optimized for rising transitions, while the second delay path uses a second number of delay elements optimized for falling transitions, allowing localized optimization rather than uniform design throughout the circuit.
2Device complexity
If DCDL circuits use traditional delay stages with equal numbers of delay elements for both signal paths, then the circuit design is simplified, but delay time linearity deteriorates due to transistor switching speed variations
Solution Approach 1:
The circuit implements local quality by configuring the first delay path with a first number of delay elements and the second delay path with a second number of delay elements, where the numbers differ to compensate for transistor switching speed variations. This unequal configuration optimizes delay time linearity for each signal transition type based on their specific characteristics rather than using a uniform design.
Solution Approach 2:
The invention changes the parameter of delay element count in each path to optimize performance. By adjusting the number of delay elements in the first and second delay paths differently, the circuit compensates for process variations and achieves better delay time linearity across different signal transitions.
3Measurement precision
If DCDL circuits use more transistors in delay stages, then the delay time control precision improves, but the circuit size increases
Solution Approach 1:
The delay stage is segmented into first and second delay paths that process rising and falling transitions separately. Each path uses a tailored number of delay elements optimized for its specific transition type, reducing the total transistor count compared to traditional designs that must accommodate both transitions with equal resources.
Solution Approach 2:
The invention optimizes the parameter of delay element count in each path to achieve the best delay time control precision with minimal transistors. By using different numbers of delay elements in each path based on their specific requirements, the circuit achieves high precision without uniformly increasing the transistor count throughout the entire circuit.
Data Source
AI summary
A digitally controlled delay line (DCDL) includes an input terminal, an output terminal, and a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal. Each stage of the plurality of stages includes a first inverter configured to selectively propagate the signal along the first signal path, a second inverter configured to selectively propagate the signal along the second signal path, and a third inverter configured to selectively propagate the signal from the first signal path to the second signal path. Each of the first and third inverters has a tunable selection configuration corresponding to greater than three output states.