Digital Delay Lock Loop Circuit for High-Frequency Phase Alignment
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Solution Overview
Problem
Conventional delay lock loop (DLL) circuits in digital systems are susceptible to unwanted latencies due to characteristics of analog circuitry, particularly at higher frequencies and with smaller feature sizes, leading to errors and distortion in phase alignment between reference and output clock signals.
Innovation Solution
The implementation of digitally controlled DLL circuits that utilize a phase detector, phase accumulator, decoder, and delay element to align clock signals, combining digital and analog circuitry to mitigate latency and improve accuracy and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional analog delay lock loop circuits are used, then the circuit can operate at basic frequencies, but unwanted latencies and errors increase at higher frequencies and smaller feature sizes
Solution Approach 1:
The patent replaces the conventional analog delay lock loop circuit with a digitally controlled delay lock loop circuit. The digital circuit uses a phase detector, digital counter, and digital delay elements instead of analog components, thereby eliminating the unwanted latencies and errors that plague analog circuits at high frequencies and small feature sizes.
Solution Approach 2:
The patent changes the operational parameters by using digital control signals to adjust delay amounts dynamically. The digital counter accumulates phase difference information and generates control words that precisely adjust the delay elements, enabling accurate phase alignment without the latencies inherent in analog parameter adjustment.
2Ease of manufacture
If analog circuitry is used in DLL circuits, then the implementation is simpler, but errors and distortion increase particularly at higher frequencies
Solution Approach 1:
The patent substitutes digital logic components for analog circuitry. The digital delay lock loop uses digital delay elements controlled by digital counter outputs, providing manufacturing precision through digital control while maintaining ease of manufacture through standardized digital logic design and integration.
Solution Approach 2:
The patent uses digital copying of phase information through the phase detector and digital counter. The phase difference between reference and output clock signals is captured as digital information, which can be precisely processed and used to control delay elements, achieving high precision phase alignment.
3Measurement precision
If digitally controlled DLL circuits are implemented, then accuracy and reliability improve, but device complexity increases
Solution Approach 1:
The patent segments the delay lock loop function into distinct digital modules: a phase detector for measuring phase difference, a digital counter for accumulating phase information, and digital delay elements for adjustment. This segmentation provides measurement precision through specialized functions while managing complexity through modular design.
Solution Approach 2:
The digital counter serves multiple functions: it accumulates phase difference information, generates control words for delay elements, and can be reset based on lock detection. This multi-functionality reduces overall device complexity by having a single component perform multiple tasks rather than requiring separate circuits for each function.
Data Source
AI summary
Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.