Digital Deskewing for Data Reception Under Clock Skew and Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in data restoration due to increasing clock skew and jitter during communication between semiconductor chips, leading to errors and increased manufacturing costs, with analog deskewing methods resulting in long lock times and power consumption issues.
Innovation Solution
A digital deskewing method and apparatus that samples data signals using a data sampling clock signal, a first edge sampling clock signal, and a second edge sampling clock signal to determine transition areas and adjust the data signal accordingly, minimizing jitter and skew through a buffer unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an analog deskewing method is used to restore data signals, then data restoration capability is improved, but lock time becomes excessively long
Solution Approach 1:
The patent replaces the analog deskewing method with a digital deskewing method. Instead of using analog circuits to detect and correct skew, the invention uses digital sampling of data signals at multiple phases and determines transition areas digitally, thereby achieving faster lock time while maintaining data restoration capability.
Solution Approach 2:
The patent changes the operating parameters by using multiple sampling phases (first through third areas) and detecting transition areas within these phases. By digitally analyzing where logic level transitions occur within the sampling windows and adjusting sampling timing based on these digital detections, the system achieves faster locking compared to continuous analog adjustment.
2Reliability
If an analog deskewing method is used to handle data signals with few logic level transitions, then data restoration is attempted, but leakage occurs and locked state cannot be maintained
Solution Approach 1:
The patent replaces the analog deskewing method with a digital deskewing method. Instead of using analog circuits to detect and correct skew, the invention uses digital sampling of data signals at multiple phases and determines transition areas digitally, thereby achieving faster lock time while maintaining data restoration capability.
Solution Approach 2:
The digital deskewing method autonomously detects transition areas and adjusts sampling timing without requiring continuous analog signal monitoring. The system self-corrects by digitally analyzing transition patterns and maintaining the locked state through digital control, eliminating the leakage issues inherent in analog methods.
3Reliability
If PCB lines or signal lines are matched to reduce skew, then data transmission quality is improved, but routing flexibility is restricted and manufacturing cost increases
Solution Approach 1:
The patent replaces physical matching of PCB lines and signal lines with a digital signal processing approach. Instead of carefully controlling physical routing to minimize skew, the invention uses digital sampling at multiple phases and software-based detection of transition areas, allowing standard routing practices while achieving skew compensation through digital processing.
Solution Approach 2:
The patent changes from physical parameter control (line length matching, impedance control) to digital parameter analysis (sampling phase selection, transition area detection). By using multiple sampling phases and digitally determining where transitions occur, the system compensates for skew without requiring precise physical routing.
4Speed
If communication speed between semiconductor chips is increased, then data transmission rate is improved, but clock skew and jitter become more severe
Solution Approach 1:
The patent implements a dynamic deskewing method that adapts to varying skew conditions. By using multiple sampling phases and dynamically determining transition areas based on actual signal behavior, the system can compensate for skew and jitter that worsen with increased communication speed, maintaining data restoration capability at higher rates.
Solution Approach 2:
The patent performs preliminary sampling at multiple phases before final data restoration. By sampling at first, second, and third areas and determining transition areas in advance, the system prepares the necessary information to correct skew and jitter before the actual data is restored, enabling high-speed communication with maintained reliability.
Data Source
AI summary
An up/down detection unit samples a received data signal and determines in which of first through third areas of the data signal the logic level of the data signal transitions, wherein the data sampling clock signal, the first edge sampling clock signal, and the second edge sampling clock signal are sequentially activated. A lower limit detection unit detects a lower limit of the first area if the logic level of the data signal transitions in the first area. An upper limit detection unit detects an upper limit of the third area if the logic level of the data signal transitions in the third area. A phase detection unit determines a delay amount indicating the amount by which the data signal is to be delayed according to the upper limit and lower limit detected. A buffer unit delays the data signal by the delay amount determined by the phase detection unit.