Digital Device Power Optimization via External Clock Frequency Configuration
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Solution Overview
Problem
Existing digital device designs consume excessive power due to assuming the external clock runs at the fastest possible speed, leading to inefficient power utilization and dissipation, as they are biased towards worst-case scenarios.
Innovation Solution
A digital device is configured to optimize power consumption by selecting operating parameters based on a desired frequency range, using a configuration register to program adjustable power and speed settings for digital functions and logic circuits, allowing them to operate efficiently over a range of external clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If digital device circuits are biased for worst-case scenario (fastest operating frequency), then the device can accommodate the fastest possible device operating frequency, but power consumption increases excessively
Solution Approach 1:
The patent applies dynamics by making the power and speed parameters adjustable rather than fixed. Configuration registers allow the digital device to dynamically select different operating modes (e.g., high-speed mode, low-power mode) based on the actual external clock frequency being used. This enables the circuits to adapt their biasing conditions to match the required operating speed, avoiding unnecessary power consumption when maximum speed is not needed.
Solution Approach 2:
The patent implements parameter changes by allowing modification of power and speed parameters through configuration registers. When the external clock frequency is determined, the system programmatically adjusts parameters such as voltage levels, bias currents, and circuit timing characteristics to optimize performance for the specific frequency range, thereby reducing power dissipation while maintaining satisfactory operation.
2Productivity
If external clock frequency is increased for faster operation, then device operating speed improves, but power dissipation increases
Solution Approach 1:
The system dynamically adjusts circuit parameters based on the actual operating frequency requirements. Configuration registers enable the digital device to select appropriate power and speed settings that match the external clock frequency being used, allowing the device to operate efficiently at lower speeds when maximum performance is not required, thus reducing power dissipation.
Solution Approach 2:
The patent enables programmable adjustment of power and speed parameters through configuration registers. By changing parameters such as voltage levels, bias currents, and timing characteristics based on the external clock frequency, the system optimizes the balance between operating speed and power dissipation, avoiding excessive energy loss when high-speed operation is not necessary.
Data Source
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AI summary
Logic circuits of a digital device may be biased to operate over specific external clock frequency ranges by programming a desired clock oscillator frequency range into a configuration memory of the digital device. In addition, clock source selection may also be programmed into the configuration register. Bias circuits are then configured so that the internal logic of the digital device will operate over the desired clock oscillator frequency range. Non-volatile memory may be used to store the contents of the configuration memory so as to retain the configuration during power down of the digital device. The non-volatile memory may be programmable fuse links, electrically erasable and programmable memory (EEPROM), FLASH memory, etc.