Digital Frequency Divider for Flexible Acceptance Windows
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Solution Overview
Problem
Conventional monitoring circuits for controllers lack flexibility in setting acceptance windows due to limitations in internal frequency dividers, leading to compatibility issues between microcontrollers and power supply chips from different manufacturers.
Innovation Solution
A digital frequency divider with adjustable division factors, including non-binary ratios and flexible acceptance windows, allowing odd divisor factors and dynamic testing capabilities through switchable diodes and feedback mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional internal frequency dividers are used in monitoring circuits, then the circuit structure is simple, but the flexibility in setting acceptance windows is limited
Solution Approach 1:
The frequency divider is segmented into multiple independent T-flip-flop stages (first, second, third T-flip-flops) that can be selectively enabled or disabled. This segmentation allows different division ratios to be achieved by activating specific combinations of stages, providing flexibility in setting acceptance windows without requiring a completely different circuit structure.
Solution Approach 2:
The circuit incorporates control signals (first control signal, second control signal, third control signal) that dynamically enable or disable specific T-flip-flop stages and coupling circuits. This dynamic control allows the acceptance window to be adjusted in real-time based on different operating conditions, transforming a static circuit into an adaptable system.
2Adaptability or versatility
If binary division ratios (powers of 2) are used, then the counter unit operation is simple, but the divider ratio is limited to specific values
Solution Approach 1:
The counter unit is divided into multiple T-flip-flop stages with different division ratios (first T-flip-flop for division by 2, second T-flip-flop for division by 3, third T-flip-flop for division by 4). By selectively coupling these stages in series, the system achieves non-binary division ratios (e.g., 1:6, 1:12, 1:24) while maintaining the simplicity of individual T-flip-flop operations.
Solution Approach 2:
Multiple T-flip-flop circuits with different division capabilities are merged through selective coupling. The output of one T-flip-flop is coupled to the input of another, creating a composite division ratio that is the product of individual divisions. This merging allows non-binary ratios while keeping each component simple to operate.
3Adaptability or versatility
If multiple divider configurations are implemented, then the acceptance window flexibility is improved, but the device complexity increases
Solution Approach 1:
The frequency divider circuit serves multiple functions: it can operate with different division ratios (1:2, 1:3, 1:4, and composite ratios like 1:6, 1:12, 1:24), support both binary and non-binary divisions, and adapt to different acceptance window requirements. This multi-functionality is achieved through a unified structure using T-flip-flops and coupling circuits that can be dynamically reconfigured.
Solution Approach 2:
The circuit is pre-configured with multiple T-flip-flop stages and coupling circuits that are ready to be activated in different combinations. Control signals pre-enable specific pathways before operation, allowing rapid switching between different division ratios without requiring complex real-time calculations or reconfiguration logic.
Data Source
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AI summary
A digital frequency divider (10) for a power supply circuit (500) of a controller (600) is disclosed. The digital frequency divider (10) comprises a counter unit (100) having a clock input (110) for a clock signal (50), a reset input (120) for a reset signal, and a plurality of outputs (130) for divider signals (Qn). The counter unit (100) is configured to generate the divider signals (Qn) as a division of the clock signal (50) by a power of 2. The digital frequency divider (10) further comprises a first coupling circuit (200) for coupling the divider signals (Qn) to a coupling signal (250), wherein the coupling signal (250) exhibits a logic HIGH only when all coupled divider signals (Qn) exhibit a logic HIGH. and a second coupling circuit (300) configured to input the coupling signal (250) into the reset input (120) of the counting unit (100).