Digital Frequency Divider Tuning for Low-Noise PLL Output
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Solution Overview
Problem
Existing phase-locked loops (PLLs) face challenges in integrating analogue and digital components effectively, leading to issues with noise amplification and reduced scalability, particularly in the design of voltage-controlled oscillators (VCOs) for wireless communication devices.
Innovation Solution
A method and apparatus for frequency tuning a signal generator output by performing frequency-dividing operations based on a control signal, where the dividing factor is determined by comparing a feedback signal with a reference signal, allowing the signal generator to operate independently of the control loop and reducing the need for noise-prone tune lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional PLL with analogue VCO and tune line is used, then frequency tuning capability is achieved, but noise is amplified and integration complexity increases
Solution Approach 1:
The patent replaces the traditional analogue voltage-controlled oscillator (VCO) with a digital frequency synthesizer that uses a phase-locked loop (PLL) and direct digital synthesis (DDS) techniques. This substitution eliminates the need for analogue tune lines and voltage-to-frequency conversion, thereby reducing noise amplification while maintaining precise frequency tuning capability through digital control mechanisms.
Solution Approach 2:
The patent introduces a digital frequency divider and programmable logic device as intermediaries between the reference clock and output signal. These components enable precise frequency control through digital division ratios rather than analogue voltage adjustment, reducing noise while achieving the required frequency tuning precision.
2Adaptability or versatility
If analogue and digital components are integrated in traditional PLL, then frequency control is achieved, but device complexity and area increase
Solution Approach 1:
The patent merges the frequency synthesis and control functions into a single integrated digital circuit block. By combining the PLL, frequency divider, and control logic into one unified digital structure, the design reduces the number of separate analogue and digital components needed, thereby simplifying integration while maintaining full frequency control capability.
Solution Approach 2:
The patent creates a universal frequency synthesis module that can generate multiple output frequencies by programmatically changing the division ratio and reference clock frequency. This multi-functional digital block replaces multiple dedicated analogue oscillators and control circuits, reducing overall device complexity while enhancing adaptability across different frequency requirements.
3Adaptability or versatility
If a wide capture range is achieved by adjusting low-pass filter cut-off frequency, then frequency tracking capability improves, but noise response increases
Solution Approach 1:
The patent implements a dynamic capture range adjustment mechanism where the effective capture range is controlled by programmatically changing the frequency division ratio rather than adjusting the low-pass filter cut-off frequency. This dynamic digital control allows the system to achieve wide frequency acquisition ranges while maintaining narrow noise filtering through the inherent stability of digital frequency synthesis.
Data Source
AI summary
A method of tuning the frequency of a generated signal to form an output signal including: forming the generated signal at a signal generator; comparing a feedback signal with a reference signal and generating a control signal in dependence on that comparison, wherein the feedback signal is generated using the output signal; and generating the output signal by performing a frequency-dividing operation in dependence on the generated signal and a dividing factor, wherein the dividing factor is determined in dependence on the control signal.