Digital DLL Delay Control Using Counters for Memory Interfaces
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Solution Overview
Problem
Existing digital delay locked loop (DLL) circuits face challenges in implementing complex control systems due to the need for phase comparison circuits and analog-digital conversions, making it difficult to achieve stable delay and high operating frequencies in memory interface circuits like DRAM.
Innovation Solution
A digital DLL circuit design that eliminates the need for phase comparison circuits by using counters and a control circuit for digital arithmetic operations to provide a delay feedback value, allowing for simple and accurate delay control without analog conversions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase comparison circuit and charge pump are used to control delay, then delay control can be achieved, but the system complexity increases and complicated control becomes difficult to implement
Solution Approach 1:
The patent replaces the analog phase comparison circuit and charge pump system with a digital counting and arithmetic operation system. The phase comparison function is substituted by counting clock cycles using counters, and the charge pump's analog voltage generation is replaced by digital arithmetic operations (subtraction and division) to calculate delay control values. This substitution of analog mechanical/electrical systems with digital systems reduces complexity while maintaining control accuracy.
Solution Approach 2:
The patent implements a digital feedback mechanism where the output signal is fed back to the counters, which measure the actual delay by counting clock cycles. The measured delay is then compared with the target delay through digital arithmetic operations, and the resulting control value is fed back to adjust the variable delay circuit. This closed-loop digital feedback system achieves accurate delay control without requiring complex analog phase comparison circuits.
2Adaptability or versatility
If multiple variable delay circuits with different delay target values are used, then versatile delay control is achieved, but multiple control systems and phase comparison circuits are required
Solution Approach 1:
The patent creates a universal delay control system where a single set of counters and a single arithmetic operation circuit can control multiple variable delay circuits with different target values. The universality is achieved by loading different target delay values into the arithmetic operation circuit as needed, allowing the same hardware infrastructure to serve multiple delay control purposes without requiring separate phase comparison circuits for each delay circuit.
Solution Approach 2:
The patent enables versatile delay control by changing the parameter (target delay value) loaded into the arithmetic operation circuit rather than changing the hardware configuration. By dynamically loading different target values into the register and arithmetic operation circuit, the system can adapt to control multiple variable delay circuits with different requirements without adding more phase comparison circuits.
3Ease of operation
If an analog-controlled variable delay circuit is used, then continuous delay adjustment is possible, but digital control and processing become difficult
Solution Approach 1:
The patent substitutes the analog-controlled variable delay circuit with a digitally-controlled variable delay circuit. Instead of using analog voltage to control delay, the system uses digital control values generated through arithmetic operations. This replacement maintains the ability to adjust delay continuously (through fine-grained digital steps) while enabling straightforward digital processing and control without requiring analog-to-digital conversion circuits.
Data Source
AI summary
A digital DLL circuit includes: a register configured to hold a delay target value; an oscillator; a first counter configured to count an external reference clock or an oscillation output from the oscillator; a second counter configured to count the oscillation output from the oscillator or the external reference clock in every measurement cycle determined by the first counter; and a digitally-controlled variable delay circuit. The DLL circuit further includes a control circuit configured to control the reset and activation of the first counter and the second counter, and control the stop of the first and second counters according to need, based on a count value of the first counter, the control circuit subjecting a count value of the second counter and the delay target value of the register to a digital arithmetic operation, and supplying the variable delay circuit with a result of the arithmetic operation as a delay control value.