Digital Delay-Locked Loop for Multi-Cycle Delay Locking
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Solution Overview
Problem
Traditional digital delay-locked loops face challenges in designing a digital delay line where the minimum delay time exceeds one clock cycle, particularly for high-speed clock signals, due to the harmonic locking problem and circuit parasitic effects.
Innovation Solution
A digital delay-locked loop comprising a frequency divider, signal selector, delay line, phase detector, and state machine, which adjusts frequency division information and delay control signals to achieve a delay time that is a multiple of the clock cycle, using a clock phase switching circuit to ensure phase alignment and flexibility in delay settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the minimum delay time of the delay line is made less than one cycle of the input clock signal to avoid harmonic locking, then the DLL can be locked to one cycle, but this approach is no longer applicable for high-speed clock signals where the minimum delay time exceeds one cycle due to circuit parasitic effects
Solution Approach 1:
The patent segments the delay line into multiple basic delay cells (N cells) that can be independently controlled. Each cell contributes to the total delay, allowing the system to achieve variable delay times including multiples of clock cycles. This segmentation enables the delay line to be configured for different clock speeds and delay requirements, resolving the contradiction between maintaining reliable locking and adapting to high-speed signals where minimum delay exceeds one cycle.
Solution Approach 2:
The patent implements dynamic control of the delay line through a state machine that adjusts the delay amount based on phase detector feedback. The delay line transitions from a fixed minimum delay configuration to a dynamically adjustable delay mechanism that can achieve locking at integer multiples of the clock cycle. This dynamic adjustment capability allows the system to adapt to high-speed clock signals while maintaining reliable locking.
2Measurement precision
If more stages of basic delay cells are used to achieve higher resolution for high-speed clock signals, then the delay precision is improved, but the minimum delay time of the whole delay line usually exceeds one cycle, causing harmonic locking problems
Solution Approach 1:
The patent employs a phase detector and state machine that form a feedback control loop. The phase detector compares the phase of the delayed signal with the reference clock, and the state machine adjusts the delay line control signal accordingly. This feedback mechanism ensures that even with multiple delay cell stages providing high resolution, the system can accurately lock to integer multiples of the clock cycle, preventing harmonic locking while maintaining delay precision.
Solution Approach 2:
The patent changes the control parameter of the delay line from a fixed minimum delay to a dynamically adjustable delay amount controlled by the state machine. By varying the delay control signal based on phase detection feedback, the system can precisely control the total delay time to achieve integer multiples of the clock cycle, resolving the contradiction between high delay resolution and accurate locking.
Data Source
AI summary
The digital delay-locked loop includes: a frequency divider, used to perform frequency division processing on a first clock-signal according to frequency division information, and output a second clock-signal; a signal-selector, used to select the first or second clock-signal as a third clock-signal according to the selection signal output; a delay line, used to delay the third clock-signal according to the delay control signal, and output a fourth clock-signal; a phase detector, used to receive the third and fourth clock-signals, perform phase detection processing, and output a phase detection judgment signal; and a state machine connected with the frequency divider, signal-selector, delay line and phase detector, used to adjust and control the frequency division information, the selection signal and the delay control signal output according to the phase detection judgment signal and a set state logic, to achieve that delay time of the fourth clock-signal relative to the first clock-signal.