Digital Delay Locked Loop With Lead-Lag Phase Control
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Solution Overview
Problem
Fully digital delay locked loops (DLLs) face challenges in achieving low complexity, low surface area, and low power consumption, leading to high design complexity and increased circuit area and power consumption.
Innovation Solution
A digital delay locked loop design featuring first and second digitally controllable delay lines coupled in series, with a time-to-digital converter evaluating phase differences to generate control signals for lead and lag portions, utilizing a selector circuit and flip-flops to encode digital signals for precise phase control, thereby reducing complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fully digital DLL is implemented, then jitter performance is improved, but design complexity and circuit area increase
Solution Approach 1:
The delay line is divided into multiple individually controllable delay elements (e.g., inverters with adjustable enable signals). Each delay element can be independently controlled to add or remove delay, allowing precise phase adjustment without requiring complex analog circuitry. This segmentation enables digital control while maintaining simplicity.
Solution Approach 2:
The delay elements are made dynamically controllable through digital control signals that can adjust the delay amount in real-time. The delay line transitions from a static structure to a dynamically adjustable one, enabling the DLL to adapt to phase errors while maintaining a relatively simple digital architecture.
2Reliability
If a fully digital DLL is implemented, then jitter performance is improved, but power consumption increases
Solution Approach 1:
Instead of continuously activating all delay elements, the control circuit selectively activates only the necessary number of delay elements required to correct the detected phase error. This partial action reduces the overall power consumption while still achieving the required phase adjustment for improved jitter performance.
3Measurement precision
If more delay elements are added to increase phase control precision, then phase control precision is improved, but circuit area increases
Solution Approach 1:
Multiple delay elements are merged into a single unified delay line structure where several delay stages share common control logic and routing infrastructure. This merging approach allows precise phase control through multiple individually controllable elements while reducing the overall circuit area compared to having separate independent delay circuits.
Solution Approach 2:
The delay elements are designed to serve multiple functions: they provide both the delay function and the phase control function. The same delay elements that introduce time delays also serve as the control mechanism for phase adjustment, eliminating the need for separate control circuitry and reducing overall circuit area.
Data Source
Figure 1~3A
Figure 3B~3D
Figure 4
AI summary
The invention concerns a digital delay locked loop comprising: first and second digitally controllable delay lines (202B, 204B) coupled in series with each other, each comprising a lead portion (214, 218) and a lag portion (216, 220), the first digitally controllable delay line receiving a reference timing signal (TREF) and the second digitally controllable delay line outputting a delayed timing signal (TREF'); and a time to digital converter (212) configured to evaluate a phase difference between the reference signal (TREF) and the delayed timing signal (TREF') and to generate a first control signal (DLEAD_[0:n]) for controlling said lead portions (214, 218) or a second control signal (DLAG[0:n]) for controlling said lag portions (216, 220) based on the sign and magnitude of the phase difference.