Digital Delay-Locked Loop with Fine Phase Adjustment for Low Jitter
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Solution Overview
Problem
Existing digital DLL circuits face challenges in precisely adjusting the delay of the output signal to one fourth of a cycle, leading to increased jitter due to discrepancies in the quantity of buffer circuits used in the phase determination and phase adjustment sections.
Innovation Solution
The digital DLL circuit incorporates a phase determination section with a delay generation unit and a determination circuit to generate a phase adjustment signal, and a phase adjustment section with variable delay units, allowing for precise adjustment of the delay time in steps of ½n the delay time of the fixed delay elements, ensuring the output signal is delayed by one fourth of a cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the quantity of buffer circuits in the phase adjustment section is set to one fourth the quantity in the phase determination section, then the output signal delay is approximately one fourth of a cycle, but the jitter reduction is insufficient due to precision discrepancies
Solution Approach 1:
The phase adjustment section is segmented into multiple sub-sections, each with buffer circuits that can be independently controlled. This allows precise adjustment of the total buffer quantity to exactly one fourth of the phase determination section, rather than using a single large-scale configuration. The segmentation enables fine-grained control over the delay precision while managing circuit complexity through modular design.
2Reliability
If the quantity of buffer circuits is increased to improve delay accuracy, then the jitter reduction improves, but the circuit complexity and area increase
Solution Approach 1:
Instead of using excessive buffer circuits to guarantee jitter reduction, the invention applies partial action by precisely calculating and implementing only the necessary one fourth quantity of buffers in the phase adjustment section. This is achieved through controlled opening and closing of switch circuits that selectively activate the exact number of buffer stages needed, avoiding unnecessary circuit area while maintaining reliable jitter performance.
3Adaptability or versatility
If switch circuits are used to control the quantity of buffer circuits, then the delay time can be adjusted, but the phase matching precision between sections deteriorates
Solution Approach 1:
The invention implements feedback mechanisms where the phase determination section monitors the actual phase difference between input and output signals, and dynamically adjusts the switch circuit control signals to maintain precise phase matching. This closed-loop control ensures that even as the buffer quantity is adjusted for delay adaptation, the phase matching precision between the phase determination and phase adjustment sections is continuously optimized and maintained.
Data Source
AI summary
A phase determination section determines the quantity of first fixed delay elements for delaying a clock signal by one cycle and generates a selection signal indicating the determination result. A phase adjustment section determines, based on the selection signal, the quantity of second fixed delay elements for delaying an input signal and generates the output signal by delaying the input signal by a certain phase amount. The phase adjustment section includes a variable delay unit which generates, based on the selection signal, a variable delay time allowing the delay time of the output signal to be adjusted in steps of ½n the delay time of one of the second fixed delay elements.