Digital DLL Circuit for Independent Rise and Fall Delay Control
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Solution Overview
Problem
Existing digital delay locked loop (DLL) circuits cannot individually control the delays of the rise and fall sides of a signal, leading to errors in clock duty and delay differences between signal edges, which affects the stability of clock access time and operating frequency in memory interface circuits.
Innovation Solution
A digital DLL circuit with separate registers for specifying rise and fall delays and a digitally-controlled variable delay circuit to independently manage these delays, ensuring accurate control and compensation of clock duty and signal edge differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single variable delay circuit is used with feedback control to a predefined delay value, then the circuit structure is simple, but the delays of rise side and fall side cannot be individually controlled
Solution Approach 1:
The single variable delay circuit is segmented into two independent variable delay circuits: one for rise-side delay control and another for fall-side delay control. Each circuit has its own delay specifying value register and control mechanism, enabling independent adjustment of rise and fall delays to compensate for duty cycle errors and delay differences
Solution Approach 2:
Different delay control characteristics are applied to different parts of the signal waveform. The rise-side delay circuit applies specific delay characteristics to the rising edge, while the fall-side delay circuit applies different delay characteristics to the falling edge, allowing optimized local control for each transition type
2Measurement precision
If separate control of rise and fall delays is implemented, then clock duty error and signal edge delay difference can be compensated, but the device complexity increases
Solution Approach 1:
Feedback control mechanisms are implemented for both rise-side and fall-side delay circuits. Each circuit receives feedback signals that enable automatic adjustment of delay values to compensate for duty cycle errors and delay differences, achieving precise control through closed-loop operation
Solution Approach 2:
The delay specifying values in the registers are treated as adjustable parameters that can be dynamically changed to optimize performance. By modifying these parameters in response to measured delay differences and duty cycle errors, the system achieves high precision control without requiring overly complex hardware
Data Source
AI summary
A digital DLL circuit includes: a first register configured to hold a first delay specifying value to specify a delay of a rising edge side of a signal; a second register configured to hold a second delay specifying value to specify a delay of a falling edge side of a signal; and a digitally-controlled variable delay circuit configured to be allowed to individually control delays of a rise side and a fall side of a signal. The digital DLL circuit further includes a control circuit configured to implement control so that a rise-side delay and a fall-side delay by the variable delay circuit are kept at the first delay specifying value of the first register and the second delay specifying value of the second register, respectively.