Digital Delay Locked Loop With Coarse-Fine Timing Alignment
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Solution Overview
Problem
Existing memory interface technologies face challenges in achieving precise timing control between memory and processing chips, particularly in double data rate systems, due to limited fine delay resolution and the complexity of implementing analog circuits in digital logic processes.
Innovation Solution
A digital delay locked loop (DLL) circuit is introduced, comprising a clock divider, phase detector, coarse and fine delay lines, and a delay control finite state machine, which allows for precise synchronization of timing signals by providing coarse and fine grained adjustments, and a low pass filter to mitigate jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If analog circuits are used to delay or compare signals in a delay locked loop, then signal delay and comparison can be achieved, but the circuits become difficult to implement and control using standard digital logic processes, requiring additional characterization and prototype work
Solution Approach 1:
The patent replaces analog circuits with digital logic circuits. Specifically, it uses digital delay elements (such as chains of logic gates or flip-flops) instead of analog delay circuits, and digital comparators instead of analog phase detectors. This substitution allows the delay locked loop to be implemented using standard digital logic processes, eliminating the need for additional characterization and prototype work while maintaining the core functionality of signal delay and comparison.
2Measurement precision
If a single delay line is used in the delay locked loop, then the circuit structure is simplified, but fine delay resolution cannot be achieved
Solution Approach 1:
The patent divides the delay line into two separate segments: a coarse delay line and a fine delay line. The coarse delay line provides large-step delay adjustments, while the fine delay line provides small-step precision adjustments. This segmentation allows the system to achieve fine delay resolution without requiring a single extremely complex delay line, as each segment can be optimized for its specific function.
Solution Approach 2:
The patent introduces a hierarchical structure to the delay control system by adding a second dimension of control: coarse control for large delay ranges and fine control for precision adjustment. This multi-dimensional approach to delay control enables the system to achieve both wide delay range and fine resolution, effectively solving the contradiction between simplicity and precision.
3Measurement precision
If more gates are used to delay the desired signal to achieve fine delay resolution, then delay precision is improved, but the number of gates increases
Solution Approach 1:
The patent segments the delay function into coarse and fine components, allowing the fine delay resolution to be achieved with a dedicated fine delay line that uses fewer gates than a single comprehensive delay line would require. The coarse delay line handles the bulk of the delay requirement, while the fine delay line adds only the necessary precision adjustments.
Solution Approach 2:
The patent implements dynamic control of the delay lines through separate control signals for coarse and fine delay elements. This dynamic segmentation allows the system to adjust the effective number of gates engaged in delay based on the required precision, optimizing the gate count for different operating conditions.
Data Source
AI summary
An efficient implementation of a digital delay locked loop (DLL) circuit is disclosed. The delay locked loop (DLL) circuit includes a phase detector circuit, a clock divider circuit, a delay, a delay control finite state machine (FSM) and an output low pass filter. The delay includes a coarse delay line and a fine delay line. The coarse delay line delays a signal by a fixed large amount and the fine delay line introduces a smaller precise delay. The delay control FSM adjusts the delay to keep the output signal of the DLL synchronized with the input. The adjustment is averaged over a range of cycle periods in order to avoid adjusting the edges of signal waveform constantly. The low pass filter at the output minimizes the jitter in the output signal.