Two-Stage Digital Down Conversion for Lower-Power RF Mixing
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Solution Overview
Problem
Conventional digital down converters (DDCs) face high complexity and power consumption due to the need for complex digital circuitry and high precision Cos/Sin computations at giga-sample per second rates, especially in dual band operations, leading to significant power consumption.
Innovation Solution
The proposed solution involves a two-stage digital mixing process with a low resolution mixer and a high resolution mixer, coupled with a decimation filter and frequency partitioning circuitry, reducing circuit complexity and power consumption by operating at lower sampling rates and using canonical signed digit vector multipliers to perform down conversions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional digital down converters use high precision Cos/Sin computations at giga-sample per second rates, then down conversion accuracy is improved, but power consumption increases significantly
Solution Approach 1:
The patent divides the down conversion process into two separate stages: a first down conversion stage that operates at giga-sample per second rates with reduced precision, followed by a second down conversion stage that operates at lower sampling rates with high precision. This segmentation allows the system to achieve overall high accuracy while significantly reducing power consumption by performing computationally intensive operations at lower rates after initial down conversion.
Solution Approach 2:
The first down conversion stage performs a preliminary frequency reduction by converting the RF signal to an intermediate frequency before the second down conversion stage. This preliminary action reduces the sampling rate requirement for the high precision computations in the second stage, thereby reducing power consumption while maintaining final output accuracy.
2Speed
If conventional digital down converters perform down conversion at giga-sample per second rates, then signal processing speed is improved, but circuit complexity increases
Solution Approach 1:
The patent segments the down conversion process into two stages with different sampling rates and complexity levels. The first stage operates at high speed with simpler circuitry, while the second stage operates at lower speed with more complex high precision computations, thereby reducing overall circuit complexity while maintaining signal processing speed.
Solution Approach 2:
The system dynamically adjusts the sampling rate between stages - the first down conversion operates at the high giga-sample per second rate of the ADC, while the second down conversion operates at a lower rate after decimation filtering. This dynamic rate adjustment optimizes the balance between processing speed and circuit complexity.
3Productivity
If conventional digital down converters use high sampling rates for down conversion, then processing capability is improved, but circuit area increases
Solution Approach 1:
The patent segments the processing into two stages: the first stage handles the high sampling rate processing at reduced precision with smaller circuit area, while the second stage performs high precision processing at lower sampling rates. This segmentation reduces the overall circuit area required compared to performing all high precision operations at the original high sampling rate.
Solution Approach 2:
The first down conversion stage performs a preliminary frequency reduction that enables subsequent decimation filtering to reduce the sampling rate before the second down conversion stage. This preliminary action reduces the processing capability requirements for the second stage, thereby reducing the circuit area needed for high precision computations.
Data Source
AI summary
A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.