Calibrated Digital Droop Detection for Adaptive Clock Delay
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Solution Overview
Problem
As semiconductor devices increase in integration and speed, power consumption also rises, leading to challenges in detecting and managing voltage droops, which can cause malfunctions, and existing digital droop detectors are vulnerable to process and temperature changes, necessitating a solution to reduce power consumption while maintaining reliable operation.
Innovation Solution
A digital droop detector that converts voltage level changes into codes, corrects nonlinearity, and adjusts clock signal delays to adapt to droop conditions, using a calibration method that compensates for process and temperature variations, allowing for reduced power supply voltage margins and improved droop detection accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high guard band is set to prevent voltage droop, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage margin adjustment by detecting voltage droop in real-time and adaptively modifying the clock signal delay. Instead of using a fixed high guard band, the system dynamically adjusts the timing margin based on actual droop conditions, allowing the voltage margin to be minimized while maintaining reliability through active monitoring and adaptive response.
2Measurement precision
If digital droop detector is used for real-time detection, then droop detection capability is improved, but vulnerability to process and temperature changes increases
Solution Approach 1:
The patent employs feedback mechanisms where the digital droop detector continuously monitors voltage droop and feeds this information back to adjust the clock signal delay. The system uses the detected droop information to dynamically modify timing parameters, creating a closed-loop control that compensates for process and temperature variations through real-time adaptation rather than relying solely on static detector accuracy.
Solution Approach 2:
The patent changes the delay parameter of the clock signal based on detected droop conditions and environmental factors. By dynamically adjusting the delay magnitude in response to process and temperature changes, the system maintains accurate droop detection capability across varying operating conditions without being vulnerable to fixed parameter limitations.
3Use of energy by moving object
If voltage margin is minimized to reduce power consumption, then power efficiency is improved, but droop detection accuracy deteriorates
Solution Approach 1:
The patent applies preliminary calibration to establish accurate baseline characteristics of the clock signal and voltage droop relationship before normal operation. This preliminary action creates a reference model that enables accurate droop detection even when the voltage margin is minimized during actual operation, decoupling the detection accuracy from the operational voltage margin.
Data Source
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AI summary
A digital droop detector (100) for detecting whether a droop occurs in a power supply voltage (VDD), may include processing circuitry (1100, 1200, 1300, 1400) configured to, detect a voltage level change of a power supply voltage (VDD) in response to a clock signal (FCLK), the detecting the voltage level change including converting the detected voltage level change into a first code (S_TAPS), correct at least one nonlinearity included in the first code (S_TAPS), the correcting including converting the first code into a second code (OUT) and a target range, and adjust a delay magnitude of the clock signal based on the second code (OUT).