Digital Duty Cycle Calibration Using Closed-Loop Phase Shifting
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Solution Overview
Problem
Existing duty cycle calibration systems face challenges such as high power consumption, complexity, and accuracy issues due to PVT mismatches, especially in high-speed clock applications, and require significant start-up time in analog systems, while digital systems struggle with jittering and edge generation.
Innovation Solution
A digital duty cycle calibration system using a closed-loop control mechanism with phase shifters and duty cycle control circuits to calibrate clock signals without analog circuitry, reducing calibration time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog duty cycle calibration systems are used, then calibration accuracy can be achieved, but significant start-up time and high power consumption are required
Solution Approach 1:
The patent replaces analog calibration circuitry with a digital calibration system that uses phase shifters, duty cycle control circuits, and digital logic to achieve duty cycle calibration. This substitution eliminates the need for analog settling time while maintaining calibration accuracy through digital measurement and control mechanisms.
Solution Approach 2:
The patent changes the operating parameters by using digital control signals to adjust phase shifters and duty cycle control circuits, replacing the continuous analog parameter adjustment with discrete digital parameter changes. This enables faster calibration without the settling time required by analog systems.
2Measurement precision
If analog duty cycle calibration systems are used, then calibration accuracy can be achieved, but high power consumption occurs
Solution Approach 1:
The patent replaces power-hungry analog calibration circuitry with a digital calibration system that uses phase shifters, duty cycle control circuits, and digital logic. This substitution significantly reduces power consumption while maintaining calibration accuracy through digital measurement and control mechanisms.
3Use of energy by moving object
If digital duty cycle calibration systems are used, then power consumption is reduced, but jittering and edge generation issues occur
Solution Approach 1:
The patent introduces phase shifters and duty cycle control circuits as intermediary components between the clock signal source and the final output. These intermediaries enable precise digital control of the clock signal edges while filtering out jitter, maintaining signal stability without requiring analog circuitry.
Solution Approach 2:
The patent implements a feedback mechanism where the duty cycle control circuits continuously monitor and adjust the clock signal based on measured duty cycle values. This closed-loop control eliminates jitter and ensures stable signal output while maintaining the power efficiency of digital circuitry.
4Measurement precision
If existing duty cycle calibration systems are used, then calibration can be performed, but complexity increases due to PVT mismatches
Solution Approach 1:
The patent segments the calibration system into distinct functional blocks: phase shifters for timing adjustment, duty cycle control circuits for duty cycle measurement and control, and digital logic for coordination. This segmentation makes the system more manageable and reduces complexity by clearly defining the function of each component in handling PVT mismatches.
Data Source
AI summary
Systems and methods for calibrating a clock signal are described. A device can include a processer, a circuit and a system duty cycle control (DCC) circuit. The circuit can perform a first phase shift on a clock signal to generate a first phase-shifted signal. The circuit can perform a second phase shift on the clock signal to generate a second phase-shifted signal. The circuit can perform a fixed DCC on the first phase-shifted signal to generate a first voltage signal. The circuit can sweep the second phase-shifted signal at a range of duty cycles to generate a second voltage signal. The circuit can sample an output clock signal at a time where the first voltage signal and the second voltage signal overlaps. The processor can generate a digital code based on the output clock signal. The system DCC circuit can calibrate the clock signal using the digital code.