All-Digital Duty Cycle Correction for Low-Voltage Clock Circuits
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Solution Overview
Problem
Existing analog duty cycle correctors face challenges in achieving effective duty cycle correction due to reduced voltage headroom in improved semiconductor processes, leading to loop locking failures and increased circuit area requirements.
Innovation Solution
An all-digital duty cycle corrector is implemented, comprising a duty cycle adjustment circuit, an asynchronous sampler, a counter, and a correction control circuit, which uses digital control codes to adjust the duty cycle of an output clock based on asynchronous sampling results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an analog duty cycle corrector utilizing RC low pass filter and operational amplifier is used, then duty cycle correction can be achieved, but circuit area increases and voltage headroom is suppressed in improved semiconductor processes
Solution Approach 1:
The patent replaces the analog duty cycle corrector (utilizing RC low pass filter and operational amplifier) with a digital duty cycle corrector that uses digital counters, logic circuits, and digital signal processing to achieve the same correction function, thereby reducing circuit area and avoiding voltage headroom suppression issues
Solution Approach 2:
The patent changes the operating parameters by switching from analog voltage-based correction to digital counting-based correction, where the duty cycle is corrected by digitally adjusting the counting threshold and comparison values rather than through analog voltage control
2Reliability
If analog signal control circuits are used to meet performance requirements, then gain and bandwidth can be achieved, but circuit area increases
Solution Approach 1:
The patent substitutes analog signal control circuits with digital logic circuits that perform equivalent functions through counting and comparison operations, eliminating the need for large-area analog components while maintaining correction performance
3Ease of operation
If operational amplifier is used in improved semiconductor processes with lower supply voltage, then duty cycle control can be implemented, but transistors enter linear region causing loop locking failure
Solution Approach 1:
The patent replaces the operational amplifier-based control system with a digital control system that uses counters and logic circuits, eliminating the transistor linear region issue entirely by operating in the digital domain where such analog limitations do not apply
Solution Approach 2:
Instead of trying to make the operational amplifier work reliably in the low-voltage environment by adjusting analog parameters, the patent inverts the approach by completely changing to a digital implementation that is inherently more suitable for low-voltage semiconductor processes
Data Source
AI summary
An all-digital duty cycle corrector and a method for correcting a duty cycle of an output clock are provided. The all-digital duty cycle corrector includes a duty cycle adjustment circuit, an asynchronous sampler, a counter and a correction control circuit. The duty cycle adjustment circuit performs duty cycle adjustment on an input clock to generate the output clock according to a digital control code. The asynchronous sampler performs asynchronous sampling on the output clock to generate N sampling results at N time points, respectively. The counter counts a number of first logic values among the N sampling results to generate a counting result. The correction control circuit compares the counting result with a reference value to generate a comparison result, and selectively adjusts the digital control code according to the comparison result, in order to correct the duty cycle of the output clock.