Digital Duty Cycle Corrector Circuit with Segmented Trim
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Solution Overview
Problem
High-speed circuits face challenges in maintaining a 50% duty cycle due to variations in process, voltage, and temperature, and existing digital duty cycle correctors suffer from inferior linearity and complexity.
Innovation Solution
A digital Duty Cycle Corrector (DCC) circuit using a control circuit with trim circuits and a single-to-differential circuit to adjust the duty cycle of input clocks, employing transistors with variable voltages and feedback mechanisms to achieve 50% duty cycle correction with improved linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a digital duty cycle corrector is used to maintain 50% duty cycle, then the circuit can operate at high speeds, but the linearity deteriorates compared to analog solutions
Solution Approach 1:
The correction range is divided into multiple segments corresponding to different trim code values. Each segment handles a specific duty cycle deviation range, with dedicated transistor pairs and trim circuits optimized for that range. This segmentation allows the digital circuit to achieve analog-like linearity within each segment while maintaining high-speed operation across the full range.
Solution Approach 2:
The circuit dynamically selects different transistor pairs and trim circuit configurations based on the measured duty cycle deviation. By dynamically adjusting which segment is active and modifying the operation of current mirrors and differential pairs, the circuit adapts to maintain optimal linearity performance across varying operating conditions and input duty cycles.
2Manufacturing precision
If traditional duty cycle correction methods are used, then the duty cycle can be corrected, but the device complexity increases
Solution Approach 1:
The same basic circuit topology and transistor pairs are used across all correction segments, with each segment reusing the same types of components (current mirrors, differential pairs, trim circuits). This universal design reduces overall complexity by eliminating the need for entirely different circuit implementations for each correction level, while still providing precise multi-level duty cycle correction.
Solution Approach 2:
The circuit automatically determines the required correction amount and applies it through the selected trim code without requiring external control logic. The duty cycle measurement and correction selection are performed autonomously by the circuit itself, eliminating the need for complex external control systems or microcontrollers.
3Manufacturing precision
If analog integrators are used for duty cycle correction, then linearity is improved, but the circuit can only operate at low speeds
Solution Approach 1:
The patent replaces the analog integrator mechanism with a digital-based correction approach using current mirrors, differential transistor pairs, and trim codes. This substitution eliminates the speed limitations of analog integrators while maintaining linearity through the segmented digital correction methodology, enabling high-speed operation with precise duty cycle control.
4Manufacturing precision
If more correction levels are added to improve linearity, then the duty cycle precision is improved, but the power consumption increases
Solution Approach 1:
The circuit provides 64 discrete correction levels through trim codes, offering fine-grained control for high precision duty cycle correction. However, not all correction levels are simultaneously active - only the appropriate segment and corresponding transistor pairs are activated based on the measured deviation, reducing overall power consumption compared to maintaining all correction paths active at once.
Data Source
AI summary
A digital duty cycle corrector circuit is provided. The duty cycle corrector circuit includes a control circuit having a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node. A single to differential circuit is connected to the control circuit at the second node. The single to differential circuit generates a first output clock and a second output clock from the duty adjusted output clock. A feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor.


