Digital Duty Cycle Adjustment Using TDC and Reduced Delay Stages

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Solution Overview

Problem

Conventional mechanisms for duty cycle adjustment in digital circuits, such as charge pumps and delay lines, face limitations in frequency range, power consumption, chip area efficiency, and noise generation, making them unsuitable for scalable and reliable pulse generation, especially in high-temperature environments.

Innovation Solution

A digital duty cycle adjustment system that utilizes a time-to-digital converter to measure and digitally adjust the duty cycle of input signals, employing a reduced number of delay stages, lower power consumption, and improved frequency response, while reducing chip area and noise, through a system comprising a time-to-digital converter, duty cycle index generator, input phase assignment generator, slave delay line, and duty cycle generator.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional charge pumps or delay lines are used for duty cycle adjustment, then duty cycle can be adjusted, but frequency range is limited and power consumption increases

Engineering Contradiction:

Improvefrequency rangeVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent replaces conventional charge pump circuits and analog delay lines with a digital time-to-digital converter (TDC) based system. The TDC measures the input signal period digitally and generates adjustment signals based on duty cycle error, substituting analog mechanisms with digital processing to achieve wider frequency range and lower power consumption

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system dynamically adjusts the duty cycle by changing the pulse width parameter based on measured duty cycle error. The TDC converts time measurements into digital codes that control the pulse generator, enabling adaptive parameter changes across wide frequency ranges without increasing power consumption

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If delay lines with more delay stages are used to support wide duty cycle adjustment range, then duty cycle adjustment range increases, but chip area increases

Engineering Contradiction:

Improveduty cycle adjustment rangeVSAvoidchip area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent replaces physical delay lines that require multiple delay stages with a digital TDC-based measurement and control system. The TDC measures time intervals digitally and generates control signals accordingly, eliminating the need for extensive delay stage networks and reducing chip area while maintaining wide duty cycle adjustment range

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system transitions from spatial adjustment (multiple delay stages in sequence) to temporal measurement (time-to-digital conversion). By measuring the input period and calculating appropriate pulse widths in the digital domain, the system achieves wide adjustment range without proportionally increasing chip area

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of operation

If conventional duty cycle adjustment mechanisms are used, then duty cycle can be adjusted, but noise generation increases

Engineering Contradiction:

Improveduty cycle adjustabilityVSAvoidnoise

Core Design Contradiction:

Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The patent replaces analog charge pump circuits that generate significant electromagnetic noise with a digital TDC-based system. The digital measurement and control approach minimizes noise generation while maintaining full duty cycle adjustability, making it suitable for sensitive digital circuits

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Area of stationary object

If circuit size scales down to improve area efficiency, then chip area decreases, but pulse generation reliability deteriorates

Engineering Contradiction:

Improvechip areaVSAvoidpulse generation reliability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent employs a digital TDC-based pulse generation system that is inherently more scalable and reliable than analog mechanisms. The digital logic and time measurement approach maintains precision and reliability even as circuit dimensions scale down, overcoming the limitations of conventional analog pulse generation in scaled technologies

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10958257B1System and method for adjusting duty cycle of a signal

Publication Date: 2021.03.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output.