Digital Duty Correction Circuit With Single-DLL Phase Blending
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Solution Overview
Problem
Conventional digital duty correction circuits require a wide layout area and high current consumption due to the need for two Delay Locked Loops (DLLs) and complex delay loops, making them unsuitable for high-speed operations and signal integrity in semiconductor devices like DDR SDRAMs.
Innovation Solution
A digital duty correction circuit that uses a repeater, delay line, phase comparator, delay controller, and phase mixer to correct distorted clock signals independently of DLLs, minimizing layout area and current consumption by performing half-phase blending to achieve a 50% duty cycle without additional DLLs or delay loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional phase mixer type digital duty correction circuit uses two DLLs to align clock signals, then high-speed operation is enabled, but layout area and current consumption increase significantly
Solution Approach 1:
The invention extracts and eliminates the redundant DLL component from the duty correction circuit. By using a single DLL instead of two, the circuit removes unnecessary complexity while maintaining high-speed operation capability, thereby reducing layout area and current consumption.
Solution Approach 2:
The invention merges the functions of two separate DLLs into a single DLL by using a phase mixer that can process both rising and falling edges of the clock signal independently. This consolidation reduces the overall circuit complexity, layout area, and power consumption while preserving high-speed performance.
2Reliability
If a conventional phase mixer type digital duty correction circuit uses two DLLs, then clock signal alignment is achieved, but device complexity increases
Solution Approach 1:
The invention extracts and removes one DLL from the conventional two-DLL configuration, reducing circuit complexity. The remaining single DLL works in conjunction with a phase mixer to achieve the same clock signal alignment function, thereby simplifying the overall device structure.
Solution Approach 2:
The phase mixer in the invention performs multiple functions: it processes both rising and falling edges of the clock signal, generates appropriate phase differences, and works with a single DLL to achieve comprehensive clock alignment. This multi-functionality reduces the need for separate dedicated circuits for each function.
3Manufacturing precision
If a conventional duty correction circuit uses two DLLs and delay loops, then duty correction is achieved, but current consumption increases
Solution Approach 1:
The invention extracts and eliminates one DLL and associated delay loops from the conventional configuration. By using a single DLL with a phase mixer that processes both clock edges, the circuit maintains duty correction precision while significantly reducing the number of active components and their associated current consumption.
Solution Approach 2:
The invention merges the duty correction functionality into a single DLL-phase mixer combination, consolidating multiple separate circuits into one integrated system. This reduction in the number of independent circuits directly lowers total current consumption while preserving correction precision.
Data Source
AI summary
The present invention relates to a duty correction circuit that corrects a distorted duty of a clock signal using a delay unit and a delay controller, thereby reducing the layout area and current consumption. The duty correction circuit includes a repeater that generates a clock signal having the same phase as that of an input clock signal with a distorted duty, and a clock signal having an inverted phase of the phase; a delay line delaying the phase of the clock signal having the inverted phase and generating a feedback clock signal; a phase comparator comparing the phase of the clock signal having the same phase with the phase of the feedback clock signal and generating a delay control signal according to the phase difference between the phases of the clock signal having he same phase and the feedback clock signal; a delay controller controlling the amount of delay of the delay line according to the delay control signal; and a phase mixer performing half-phase blending on the clock signal having the same phase and the feedback clock signal and outputting a clock signal having a corrected duty.