Digital Edge Interpolator for Calibration-Free DTC Phase Alignment

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Digital Polar Transmitter (DPTX) architectures face challenges in handling wideband signals due to misalignment between coarse and fine delay/phase segments, requiring elaborate calibration techniques and affecting noise floor requirements, especially in multi-protocol communication devices.

Innovation Solution

A Digital-to-Time Converter (DTC) architecture with a digitally controlled edge interpolator (DCEI) that generates self-aligned fine delay/phase signals without the need for calibration, ensuring frequency independence and true phase interpolation between coarse and fine segments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional coarse/fine delay segments are used in DTC, then phase modulation capability is achieved, but misalignment between coarse and fine segments occurs requiring elaborate calibration techniques

Engineering Contradiction:
Improvephase alignment accuracyVSAvoidcalibration technique complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The fine delay segment is designed to be self-aligned with the coarse delay segment through inherent circuit design. The fine delay cells are derived from the same clock network as the coarse delay cells, ensuring automatic synchronization without requiring external calibration mechanisms. This self-service approach eliminates the need for elaborate calibration techniques while maintaining precise phase alignment.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The delay line is divided into coarse and fine segments, where the coarse segment provides broad phase coverage and the fine segment provides precise phase adjustment. The segmentation is designed such that the fine segment operates within the transition region between adjacent coarse delay steps, ensuring continuous and aligned phase coverage across the entire range without calibration requirements.

Inventive Principle:
Principle #1Segmentation

2Use of energy by moving object

If DPTX architecture is used for wideband signals, then reduced size and power consumption are achieved, but bandwidth handling capability is insufficient

Engineering Contradiction:
Improvepower consumptionVSAvoidwideband signal handling capability
Core Design Contradiction:
Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The DTC implements a dynamic delay adjustment mechanism where both coarse and fine delay values can be independently controlled and updated. This dynamic capability allows the system to adapt to different signal bandwidths and frequencies in real-time, enabling wideband signal handling while maintaining the power efficiency of the digital architecture. The fine delay cells provide continuous adjustment within each coarse delay step, enhancing adaptability across wide frequency ranges.

Inventive Principle:
Principle #15Dynamics

3Object-affected harmful factors

If quantization noise level is reduced to meet noise floor requirements, then receiver desensitization is avoided, but device complexity increases

Engineering Contradiction:
Improvereceiver desensitizationVSAvoidDTC structure complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent introduces a temporal dimension to phase control by implementing fine delay adjustment within the time domain. Instead of increasing spatial complexity through more phase bits, the fine delay cells provide additional temporal resolution by interpolating between coarse delay steps. This dimensional approach reduces quantization noise without significantly increasing device complexity, as the fine delay mechanism reuses existing circuit resources.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentEP2833548B1Digitally controlled edge interpolator (DCEI) for digital-to-time converters (DTC)
Publication Date: 2018.08.22 INTEL CORP
  • EP2833548B1 patent drawingFigure 1
  • EP2833548B1 patent drawingFigure 2
  • EP2833548B1 patent drawingFigure 3A~3B

AI summary

A Digital-to-Time (DTC) for a Digital Polar Transmitter (DPT) comprises a coarse delay/phase segment and a fine delay/phase segment. The coarse delay/phase segment generates an even delay/phase signal and an odd delay/phase signal. The fine/phase delay segment receives the even coarse phase signal and the odd coarse phase signal, and is responsive to a fine delay/phase control signal to generate a fine delay/phase output signal that is an interpolation of the even delay/phase signal and the odd delay/phase signal. In one exemplary embodiment, the fine delay/phase control signal comprises a binary signal having 2N values, and the fine delay/phase segment comprises 2N interpolators. Each interpolator is coupled to the even and odd coarse phase signals and is controlled by the fine delay/phase control signal to be responsive to the even coarse phase signal or the odd coarse phase signal based on a value of the fine delay/phase control signal.