Digital Excess Loop Delay Compensation in CT Delta-Sigma Modulators
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Solution Overview
Problem
Continuous time delta sigma modulators suffer from excess loop delay and power consumption issues due to conventional compensation methods, which require additional DACs and impose timing constraints on dynamic element matching (DEM) and quantizer operations.
Innovation Solution
A novel design incorporating a fully digital ELD compensator and DEM module that operates on delayed digital codes, reducing power consumption and relaxing timing constraints by changing the ELD compensator from an analog current DAC to a fully digital circuit, and implementing DEM based on delayed digital codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an additional DAC and delay buffers are used to compensate ELD, then ELD compensation is achieved, but power consumption increases
Solution Approach 1:
The patent replaces the conventional analog current DAC-based ELD compensator with a fully digital circuit implementation. The digital ELD compensator uses delay elements and adders to compensate for excess loop delay, eliminating the need for additional physical DAC hardware and reducing power consumption while maintaining ELD compensation functionality.
2Productivity
If DEM and quantizer operations are performed within the same half clock cycle, then timing constraints are met, but power consumption increases to speed up operations
Solution Approach 1:
The patent segments the DEM and quantizer operations into separate time slots within the clock cycle. The DEM operation is performed in the first half of the clock cycle, and the quantizer operation is performed in the second half. This temporal segmentation allows each operation to complete at its natural speed without requiring power-intensive speed-up measures, while still meeting overall timing requirements.
3Manufacturing precision
If conventional ELD compensation with DEM is implemented, then component mismatch is compensated, but timing constraints become too high
Solution Approach 1:
The patent performs the DEM operation before the quantizer operation within the clock cycle. By completing the DEM (dynamic element matching) operation in advance during the first half of the clock cycle, the system prepares the randomized digital code that compensates for component mismatch, allowing the quantizer to operate in the second half without stringent timing constraints.
Data Source
AI summary
A continuous time delta sigma modulator is described in this application. In one example, the continuous time delta sigma modulator includes: a quantizer, a buffer module, a randomizer, and a reference module. The quantizer includes a comparator that generates a digital output based on a comparison of a reference potential with an input generated based on a sample of an analog signal. The buffer module stores the digital output for a predetermined delay period and outputs the digital output after the predetermined delay period as a delayed digital output. The randomizer randomizes the delayed digital output to generate a randomized digital output. The reference module modifies the reference potential based on the randomized digital output.