Digital Fail-Bit Counting Circuit With Unary-to-Binary Transcoding
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Solution Overview
Problem
Existing Verify Fail bit Count (VFC) circuits in memory devices occupy space and increase power consumption, and their analog methods for sensing failbit numbers are prone to undercounting due to factors like power drop, transistor mismatch, and signal routing issues.
Innovation Solution
A digital VFC circuit comprising a counter circuit and a transcoder circuit, where the counter circuit counts fail bits in unary format and the transcoder circuit transcodes the count result to binary format, improving accuracy and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog method is used to sense failbit numbers, then power consumption is reduced, but measurement precision deteriorates due to undercounting from power drop, transistor mismatch, and signal routing issues
Solution Approach 1:
The patent replaces the analog sensing method with a digital counting method. Instead of using analog current sensing that is susceptible to power drop and transistor mismatch, the invention uses digital counters to accurately count failbits. This substitution of analog with digital systems resolves the measurement precision issue while maintaining acceptable power consumption through efficient digital circuit design.
Solution Approach 2:
The patent changes the parameter representation from analog current values to digital count values. By converting the failbit detection from an analog measurement (prone to errors) to a digital parameter (exact counting), the measurement precision is dramatically improved. The digital domain eliminates the cumulative errors associated with analog signal degradation through power drop and routing issues.
2Reliability
If VFC circuit is added to memory device, then failbit counting capability is improved, but device area increases
Solution Approach 1:
The patent divides the memory device into multiple sections, with each section having its own dedicated VFC circuit. This segmentation allows each counter to handle a subset of failbits, reducing the complexity and area of individual circuits. The segmented approach maintains high reliability through accurate counting in each section while minimizing the total area by distributing the counting function across multiple smaller units rather than one large circuit.
3Reliability
If analog current sensing is used, then power consumption is lower, but reliability deteriorates due to undercounting leading to yield loss
Solution Approach 1:
The patent replaces the unreliable analog current sensing system with a reliable digital counting system. The digital counter provides exact failbit counts without the undercounting problems inherent in analog methods. This substitution accepts higher power consumption as a trade-off for the significant improvement in reliability and yield, as accurate failbit counting prevents defective devices from being mistakenly classified as good.
Data Source
AI summary
A verify failbit count (VFC) circuit includes a counter circuit and a transcoder circuit. The counter circuit includes a counter. The counter is configured to count one or more fail bits based on results of a verification operation of a memory device to obtain a count result in unary format. The transcoder circuit includes a transcoder coupled to the counter. The transcoder is configured to transcode the count result in unary format to a transcoded result in binary format.