Digital Fault Detection Circuit for IC Security
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Solution Overview
Problem
Integrated circuits, particularly security-relevant ones like smart cards, are vulnerable to manipulation and attacks through ionizing radiation, supply voltage fluctuations, and signal probing, which existing protection methods fail to adequately address.
Innovation Solution
A digital fault detection circuit is designed with a minimal number of circuit elements, including an input circuit, a keeper circuit, and fault detector cells, which sets and maintains a signal state and changes it in response to faults, mimicking the behavior of regular digital circuits to detect attacks effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing protection methods are used, then integrated circuits can be protected to some extent, but they fail to adequately address manipulation and attacks through ionizing radiation, supply voltage fluctuations, and signal probing
Solution Approach 1:
The patent introduces a digital fault detection circuit as an intermediary system between the integrated circuit and external attack vectors. This detection circuit monitors the integrated circuit for signs of manipulation through ionizing radiation, supply voltage fluctuations, or signal probing, and triggers appropriate responses without directly blocking the attacks, thereby addressing the vulnerability while maintaining circuit functionality.
Solution Approach 2:
The patent implements a feedback mechanism where the digital fault detection circuit continuously monitors the integrated circuit's operation and responds to detected faults. When manipulation or attacks are detected, the system provides feedback signals that can alter the integrated circuit's behavior or alert external systems, thereby improving security against the harmful factors mentioned.
2Reliability
If comprehensive protection against all attack methods is implemented, then security is improved, but the circuit complexity and area requirements increase
Solution Approach 1:
The patent designs a universal digital fault detection circuit that can detect multiple types of attacks and manipulation methods through a single integrated system. The detection circuit uses general monitoring mechanisms that can identify ionizing radiation effects, supply voltage fluctuations, and signal probing attempts, eliminating the need for separate dedicated protection circuits for each attack vector and thereby reducing overall complexity.
Solution Approach 2:
The patent merges multiple protection functions into a single digital fault detection circuit. Instead of implementing separate protection mechanisms for different attack types, the system combines monitoring, detection, and response functions into one integrated unit, reducing the total number of circuit elements while maintaining comprehensive security coverage.
3Measurement precision
If a digital fault detection circuit is added to enhance security, then fault detection capability is improved, but the area requirements and manufacturing costs increase
Solution Approach 1:
The patent uses a simplified digital fault detection circuit that replicates the essential monitoring function of the integrated circuit using a minimal set of digital logic elements. By creating a lightweight copy of the detection functionality rather than a full-scale replica, the system achieves high fault detection sensitivity while minimizing the additional chip area required.
Solution Approach 2:
The patent employs a cost-effective digital fault detection circuit that uses standard digital logic components rather than expensive specialized hardware. The detection circuit is designed to be implemented using conventional CMOS technology with minimal additional area, making the security enhancement economically viable while maintaining high detection capability.
Data Source
AI summary
Digital fault detection circuit with an input circuit having input and output, wherein a first signal state at the input causes a predetermined signal state at the output and a second signal state at the input leaves the output floating; a signal line with signal line input and output, wherein the signal line input is coupled to the output of the input circuit; a keeper circuit coupled to the signal line output and configured to keep the signal line at the predetermined signal state, after the signal state at the input has changed from the first signal state to the second signal state; and a fault detector cell, which is coupled to the signal line between the signal line input and the signal line output and which is configured to change the state of the signal line which is otherwise kept by the keeper circuit, in response to a fault.