Digital Fault Detection System for Integrated Circuits
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Solution Overview
Problem
Conventional fault detection systems in integrated circuits (ICs) are limited in detecting various types of fault injection attacks, such as power glitching and electromagnetic attacks, due to their exclusive analog component design, which occupies significant area and increases complexity, making them vulnerable to other attack types and reducing fault coverage.
Innovation Solution
A digital fault detection system within a predefined distance of the functional system, utilizing state and toggle registers, error detection code (EDC) registers, logic circuitry, and EDC generators, synchronized with separate clock signals to detect faults across multiple types of attacks without modifying the functional system, thereby reducing complexity and increasing fault coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional fault detection system uses analog components (voltage reference generators, delay lines), then it can detect power glitching attacks, but it occupies significant area on the IC and limits the number of fault detection systems that can be included
Solution Approach 1:
The patent replaces the conventional analog fault detection system with a digital fault detection system. The digital system uses digital components (registers, logic circuits, EDC generators) instead of analog components (voltage reference generators, delay lines) to detect faults. This substitution reduces the area occupancy significantly while maintaining fault detection capability across multiple attack types including power glitching, electromagnetic fault injection, and clock glitching attacks.
2Reliability
If a fault detection system is integrated with the functional system to enable fault detection, then fault detection is possible, but the functional system must be modified leading to increased complexity
Solution Approach 1:
The patent segments the fault detection function from the functional system by placing the digital fault detection system within a predefined distance of the functional system rather than integrating it directly. This segmentation allows the fault detection system to monitor the functional system independently without requiring modifications to the functional system's architecture. The fault detection system can detect faults in the functional system while maintaining its own operational independence, thereby reducing overall system complexity.
3Adaptability or versatility
If a fault detection system uses analog components, then it can detect power glitching attacks, but it is vulnerable to other types of fault injection attacks (e.g., electromagnetic fault injection attacks)
Solution Approach 1:
The patent implements a universal digital fault detection system that can detect multiple types of fault injection attacks including power glitching attacks, electromagnetic fault injection attacks, and clock glitching attacks. The digital system uses EDC generators and comparators that can identify various fault patterns regardless of their origin, providing broad coverage against different attack vectors. This multi-functional capability makes the system adaptable to various attack types without requiring separate detection mechanisms for each attack type.
Data Source
AI summary
A fault detection system includes a state register, an error detection code (EDC) register, logic circuitry, an EDC generator, and an EDC checker. The state and EDC registers store first reference data and first checksum data, respectively. The logic circuitry executes a logic function based on the first reference data to iteratively generate second reference data that is different from the first reference data, and updates the first reference data of the state register with the second reference data of one iteration. The EDC generator iteratively generates second checksum data based on the iteratively generated second reference data and updates the first checksum data of the EDC register with the second checksum data of one iteration. The EDC checker detects a fault in the IC based on the updated first reference data and the updated first checksum data.