Digital Feed-Forward Data Recovery Using Free-Running Sampling Clock
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Solution Overview
Problem
High-speed communication systems face challenges in clock and data recovery due to large die size, high power consumption, and limitations of analog PLLs, while digital PLLs suffer from speed tracking limitations and inter-symbol interference (ISI).
Innovation Solution
Implementing a digital feed-forward data recovery method using a free-running sampling clock, which oversamples data with multi-phase clocks, packs samples into data blocks, tracks data transitions, and determines a decision window to make symbol bit decisions, thereby achieving faster locking and improved ISI immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog PLLs are used for clock and data recovery, then data recovery can be achieved, but die size becomes large and power consumption increases
Solution Approach 1:
The patent replaces the analog PLL mechanical/electrical system with a digital system using discrete logic elements. The free-running counter generates sampling clocks digitally, and digital circuitry performs data sampling and transition detection, eliminating the need for analog components like VCOs and loop filters, thereby reducing die size.
Solution Approach 2:
The patent extracts and eliminates the feedback loop component from the traditional PLL architecture. By using a free-running counter without feedback to generate sampling clocks, the design removes the loop filter and associated analog components that consume area and power, while maintaining data recovery functionality through digital transition detection.
2Reliability
If analog PLLs are used for clock and data recovery, then data recovery can be achieved, but power consumption becomes high
Solution Approach 1:
The patent substitutes analog circuitry with digital logic, where free-running counters and digital sampling circuits consume significantly less power than analog VCOs and loop filters. The digital transition detection logic requires minimal power compared to the continuous analog signal processing in traditional PLLs.
Solution Approach 2:
By removing the feedback loop and loop filter from the architecture, the patent eliminates the primary sources of power consumption in analog PLLs. The free-running counter generates clocks without requiring the continuous power-hungry analog components of a traditional PLL.
3Area of stationary object
If digital PLLs are used for clock and data recovery, then die size is reduced, but tracking speed becomes limited
Solution Approach 1:
The patent uses a free-running counter that continuously generates sampling clocks at a predetermined rate without waiting for feedback. This preliminary action of pre-generating clocks enables the system to immediately sample incoming data and detect transitions, achieving fast locking without the speed limitations of feedback-based digital PLLs.
Solution Approach 2:
Instead of using feedback to adjust clock timing as in traditional PLLs, the patent inverts the approach by using a fixed free-running counter and detecting data transitions directly. This inversion eliminates the feedback delay mechanism that limits tracking speed in digital PLLs.
4Area of stationary object
If digital PLLs are used for clock and data recovery, then die size is reduced, but susceptibility to ISI increases
Solution Approach 1:
The patent merges the clock generation and data sampling functions into a unified free-running counter architecture. The same counter that generates sampling clocks also provides the timing reference for data decision, ensuring optimal sampling points that are immune to ISI. This combined approach eliminates the separate clock recovery path in digital PLLs that is vulnerable to ISI.
Solution Approach 2:
The free-running counter continuously prepares sampling clocks in advance without waiting for feedback, ensuring that data is sampled at the optimal point in each bit period before ISI from adjacent bits can corrupt the signal. This preliminary sampling action provides inherent immunity to inter-symbol interference.
Data Source
AI summary
Systems and methods are disclosed for improving digital feed-forward data recovery of high speed data from a received data stream in a data transceiver or receiver where the receiver clock is asynchronous to the transmitter clock used to transmit the received data stream. In one example, the received data stream is oversampled using N evenly-spaced multi-phase clocks. The oversampled data are packed into a data block. Data transition edges of the oversampled data in the data blocks with respect to multi-phase clocks are tracked. The tracked data transition edges are used to determine the length of a decision window and to further divide the oversampled data into groups of bits that are hypothesized to be samples of the same received data symbol. Bit mapping is performed on the decision window to recover the received data symbol. By tracking the movement of data transition edges, the technique enhances data recovery capability.