Variable Bit-Width Digital Filter Multipliers for Lower Power
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Solution Overview
Problem
Existing digital filters, both non-adaptive and adaptive, are inefficient in terms of area and power consumption due to assuming worst-case bit-widths for both incoming data samples and filter coefficients, leading to suboptimal implementation in modern communication systems.
Innovation Solution
The method involves determining the bit-width of incoming data samples and filter coefficients using probability distribution functions (PDFs) to allocate them to variable bit-width multipliers, reducing the number of bits required for processing and thereby minimizing area and power consumption while maintaining system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If worst-case bit-widths are assumed for all incoming data samples and filter coefficients, then system performance is maintained, but area and power consumption increase
Solution Approach 1:
The patent applies local quality by assigning different bit-widths to different multipliers based on the actual precision requirements of their specific incoming data samples and filter coefficients. Instead of uniformly using worst-case bit-widths for all multipliers, the system dynamically determines the appropriate bit-width for each multiplier by analyzing the statistical properties (PDFs) of the input signal and coefficients, thereby reducing power consumption while maintaining necessary precision where required.
Solution Approach 2:
The patent changes the parameter of bit-width from a fixed worst-case value to a dynamically adjustable parameter based on statistical analysis. By computing probability distribution functions of incoming data samples and filter coefficients, the system adapts the bit-width parameter for each multiplier to match the actual precision requirements, resolving the contradiction between maintaining system performance and reducing power consumption.
2Reliability
If worst-case bit-widths are assumed for all incoming data samples and filter coefficients, then system performance is maintained, but implementation area increases
Solution Approach 1:
The patent implements local quality by configuring each multiplier with a bit-width that matches the specific precision requirements of its operands. By analyzing the probability distribution functions of incoming data samples and filter coefficients, the system assigns appropriate bit-widths to different multipliers, avoiding the area overhead of using uniform worst-case bit-widths across all multipliers while maintaining system performance.
Solution Approach 2:
The patent dynamically adjusts the bit-width parameter for each multiplier based on statistical analysis of the input signal and coefficients. This parameter change allows the implementation area to be optimized by allocating resources according to actual precision needs rather than uniformly provisioning for worst-case scenarios, thereby reducing total implementation area while preserving system performance.
3Use of energy by stationary object
If variable bit-width multipliers are used based on statistical properties, then area and power consumption are reduced, but implementation complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-computing the probability distribution functions of incoming data samples and filter coefficients before allocating them to multipliers. This statistical analysis is performed in advance to determine the appropriate bit-width for each multiplier, allowing the system to reduce power consumption through optimized bit-width allocation without requiring complex real-time adjustments during filter operation.
Solution Approach 2:
The system performs self-service by automatically determining the bit-width requirements through statistical analysis of its own input signals and coefficients. The patent implements self-configuration of multiplier bit-widths based on the computed probability distribution functions, eliminating the need for external manual configuration or complex control logic, thereby reducing implementation complexity while achieving power savings.
4Area of stationary object
If variable bit-width multipliers are used based on statistical properties, then implementation area is reduced, but implementation complexity increases
Solution Approach 1:
The patent reduces implementation area by pre-computing the probability distribution functions and determining optimal bit-width allocations before implementing the filter. This preliminary statistical analysis enables the system to configure multipliers with appropriate bit-widths, reducing the total implementation area without requiring complex runtime reconfiguration logic.
Solution Approach 2:
The system achieves self-configuration of multiplier bit-widths by automatically analyzing the statistical properties of its inputs and coefficients. This self-service approach allows the system to optimize its own implementation area through statistical analysis without external intervention or complex control mechanisms, balancing area reduction with manageable implementation complexity.
Data Source
AI summary
A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.