Digital Filter Bandwidth Calibration for Phase Jitter Control
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Solution Overview
Problem
Phase jitter in electronic circuits varies significantly across semiconductor dies due to factors like DCO phase noise, TDC resolution, and loop bandwidth, necessitating improved control methods.
Innovation Solution
An electronic circuit with a digital filter and jitter optimization device that generates parameters to optimize bandwidth and reduce phase jitter through continuous parameter adjustment, using a gear shifting function for calibration and minimizing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase jitter control is implemented using fixed parameters, then the circuit operation is simple, but the phase jitter varies significantly across semiconductor dies
Solution Approach 1:
The patent implements dynamic adjustment of loop bandwidth parameters through a calibration sequence that measures phase jitter and automatically optimizes digital filter parameters (alpha and rho) for each semiconductor die. This transforms the fixed-parameter system into an adaptive one that compensates for die-to-die variations in DCO phase noise and TDC resolution characteristics.
Solution Approach 2:
The patent changes the parameters of the digital filter (specifically the alpha and rho coefficients) based on measured phase jitter characteristics of each die. By adjusting these parameters during calibration, the system optimizes loop bandwidth to minimize phase jitter for each specific semiconductor die, thereby resolving the variation issue.
2Reliability
If loop bandwidth is optimized for each die, then phase jitter is reduced, but the device complexity increases due to calibration requirements
Solution Approach 1:
The patent implements a self-calibrating system where the phase jitter measurement and optimization process is performed automatically by the circuit itself during initialization. The calibration sequence uses the circuit's own components (TDC, DCO, digital filter) to measure and optimize its performance without requiring external test equipment or complex additional hardware, thereby limiting the increase in device complexity.
3Manufacturing precision
If digital filter parameters are adjusted continuously, then phase jitter variation is reduced, but hardware complexity increases
Solution Approach 1:
The patent adjusts the digital filter parameters (alpha and rho) in discrete steps during calibration based on measured phase jitter values. This approach achieves reduction in phase jitter variation across dies while avoiding the need for continuous parameter adjustment mechanisms, thereby limiting hardware complexity increase.
Data Source
AI summary
An electronic circuit and a method for operating the electronic circuit are provided. The electronic circuit includes a digital filter and a jitter optimization device. The digital filter is configured to receive a first signal and generate a second signal by filtering the first signal. The jitter optimization device is configured to receive the second signal and generate a first parameter and a second parameter according to the second signal. The jitter optimization device is configured to provide a first feature and a second feature associated with the second signal, and the first parameter and the second parameter are generated in response to the first feature or the second feature.