Digital Filter Memory Layout for Parallel Reads and RAM Balance
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Solution Overview
Problem
Existing digital filters face inefficiencies in memory utilization due to capacity restrictions in RAM, leading to unnecessary large RAM sizes when using dual port SRAM for simultaneous coefficient and delay data access.
Innovation Solution
A digital filter configuration with two separate RAM units for storing coefficient and delay data, allowing parallel read operations to optimize memory usage, enabling efficient storage and switching of multiple coefficient sets for instantaneous filter characteristic changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual port SRAM is used for simultaneous coefficient and delay data access, then parallel read operations are enabled, but memory area becomes large and inefficient
Solution Approach 1:
The patent divides the memory system into two separate single-port SRAM units (first SRAM and second SRAM) instead of using one dual-port SRAM. Each SRAM is optimized for specific data types (coefficient data or delay data), reducing individual memory area while enabling parallel access through simultaneous operation of both SRAMs
Solution Approach 2:
Each SRAM unit serves multiple functions: the first SRAM stores both coefficient data for first filter and delay data for second filter, while the second SRAM stores coefficient data for second filter and delay data for first filter. This cross-storing strategy enables flexible parallel access patterns
2Productivity
If separate coefficient RAM and delay RAM are used, then operational efficiency improves, but RAM capacity becomes larger than necessary due to capacity restrictions
Solution Approach 1:
The patent makes each SRAM unit multi-functional by having it store different types of data for different filters. The first SRAM handles coefficient data for first filter and delay data for second filter, while the second SRAM handles the opposite assignments, allowing both filters to operate simultaneously with optimized memory usage
Solution Approach 2:
The patent combines the storage of coefficient data and delay data into a unified two-SRAM architecture where both data types are distributed across the two memory units. This merging approach eliminates the need for separate dedicated RAMs for each data type while maintaining operational efficiency
Data Source
AI summary
A digital filter has a plurality of filters, wherein each filter performs coefficient multiplication and delay processing for an input signal and an output signal, obtains the output signal from the input signal, and includes a plurality of coefficient multipliers for multiplying a signal by a predetermined coefficient. The digital filter also includes a plurality of delay circuits for delaying a signal, and an adder for adding a plurality of signals. A first RAM stores a plurality of sets of coefficient data for a plurality of coefficient multipliers of the first filter and stores delay data for the delay circuit of the second filter. A second RAM stores a plurality of sets of coefficient data for a plurality of coefficient multipliers of the second filter and stores delay data for the delay circuit of the first filter.