Time-Multiplexed Digital Filter Structure for Multi-Channel ANC
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Solution Overview
Problem
Existing digital filter structures require significant physical area, increased latency, and higher power consumption when implementing multiple filter stages or processing multiple channels, which is particularly problematic in consumer devices where silicon area is limited and battery life and responsiveness are critical.
Innovation Solution
A digital filter structure that operates at a higher clock rate than the input signals, utilizing a plurality of delay elements and multiplexing circuitry to selectively engage delay elements and perform filter operations on different data streams at every clock cycle, allowing for reuse across various filter orders and channels, thereby reducing hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple filter stages or multiple channels are implemented using traditional digital filter structures, then the filtering capability and processing capacity are improved, but the physical area occupied by the filter increases significantly
Solution Approach 1:
The patent merges multiple filter stages and multiple channel processing into a single integrated digital filter structure. The filter structure processes multiple channels sequentially through time-multiplexing, where a single set of filter coefficients and processing units handles different channels at different time slots, eliminating the need for separate parallel filter structures for each channel.
Solution Approach 2:
The digital filter structure is designed to perform multiple functions: it can process different numbers of channels (e.g., 2, 4, 8 channels) and different filter orders (e.g., 1st, 2nd, 3rd order) using the same hardware resources. The filter adapts its behavior through configuration settings, making it a universal solution that replaces multiple specialized filter structures.
2Adaptability or versatility
If multiple filter stages or multiple channels are implemented using traditional digital filter structures, then the filtering capability is improved, but the latency increases
Solution Approach 1:
The filter employs periodic time-multiplexed operation where different channels are processed in sequential time slots within each frame. This periodic structure allows the filter to cycle through multiple channels systematically, completing all processing within a defined time window, thereby controlling and minimizing overall latency while maintaining multi-channel capability.
3Adaptability or versatility
If multiple filter stages or multiple channels are implemented using traditional digital filter structures, then the filtering capability is improved, but the power consumption increases
Solution Approach 1:
The patent combines multiple filter processing functions into a single power-efficient structure. By processing multiple channels sequentially rather than in parallel, the filter activates processing units only when needed for each channel, reducing overall power consumption compared to maintaining multiple simultaneously active parallel filter structures.
4Area of stationary object
If a single digital filter structure is used to process multiple channels sequentially, then the hardware requirements are reduced, but the processing speed for each individual channel may be affected
Solution Approach 1:
The filter structure dynamically adapts its operation mode based on the number of channels and filter order requirements. It uses dynamic time-multiplexing where the processing schedule is adjusted according to the specific configuration, allowing optimal processing speed for each channel while sharing hardware resources efficiently. The filter can switch between different operational configurations without hardware changes.
Data Source
AI summary
A digital filter structure and related method of digital filtering are presented. The digital filter structure is arranged to receive one or more clocked input signals having a first clock rate, and which is driven at a second clock rate higher than said first clock rate. The digital filter structure has a plurality of delay elements and multiplexing circuitry arranged to selectively engage the delay elements such that, at every clock cycle of the digital filter structure, a filter operation is performed on a different stream of data. The disclosure can be applied in many different contexts. One particular implementation example is that of an adaptive noise cancellation (ANC) system using sigma-delta infinite impulse response filters. In this context the present disclosure minimizes latency and hardware implementation area by requiring only one filtering circuit for multiple channels of data to be filtered.