Digital Filter Data Rearrangement Using Dual-Port RAM Pipelines
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Solution Overview
Problem
Existing FFT/IFFT processing systems require large circuit scales and high power consumption due to the need for significant data rearrangement and storage capacity, especially when handling large numbers of points, which complicates the circuit design and increases power consumption.
Innovation Solution
A digital filter device with a data rearrangement processing unit that utilizes dual-port RAM circuits and a pipeline circuit system to efficiently rearrange data between sequential and bit reverse orders, reducing the need for large storage capacity and minimizing circuit scale and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of points FFT/IFFT processing is performed using conventional methods, then processing capability is improved, but circuit scale and power consumption increase significantly
Solution Approach 1:
The patent divides the FFT/IFFT processing into multiple stages, with each stage handling a portion of the data flow. The data rearrangement processing unit is segmented into multiple functional blocks that process data in sequential order, allowing the overall large-scale processing to be achieved through composition of smaller, more manageable circuit stages.
Solution Approach 2:
The patent introduces a time dimension to the processing architecture by implementing sequential data rearrangement across multiple clock cycles. Instead of performing all rearrangements simultaneously in parallel (which would require large circuit scale), the system performs rearrangements in sequence over time, reducing the instantaneous circuit complexity while maintaining overall processing capability.
2Ease of operation
If data rearrangement is performed using conventional RAM circuits, then data ordering is achieved, but storage capacity requirements increase
Solution Approach 1:
The patent performs data rearrangement in advance during the input phase, organizing data into the required order before subsequent processing stages. The data rearrangement processing unit reorders incoming data sequentially as it is written to storage, so that when data is read for processing, it is already in the correct order, eliminating the need for additional rearrangement operations and reducing storage capacity requirements.
Solution Approach 2:
The patent implements continuous data flow processing where data rearrangement, storage, and processing occur in an unbroken sequence. The dual-port RAM structure allows simultaneous write and read operations, maintaining continuous useful action without idle cycles, which optimizes the utilization of storage capacity and reduces the total storage needed.
3Device complexity
If iterative processing is used to achieve large-scale FFT, then processing is achieved with smaller circuits, but processing time increases
Solution Approach 1:
The patent ensures continuous processing by implementing a pipeline architecture where data rearrangement, storage, and processing occur in continuous sequence without idle cycles. The dual-port RAM enables simultaneous write and read operations, allowing the iterative processing stages to overlap in time, thereby reducing total processing time while maintaining smaller circuit scale.
Solution Approach 2:
The patent introduces dynamic control signals that coordinate the sequential operation of multiple processing stages. Control signals dynamically manage the timing and sequencing of data rearrangement and processing operations across clock cycles, optimizing the throughput of iterative processing and reducing overall processing time while keeping individual circuit stages compact.
Data Source
AI summary
A digital filter device including a data rearrangement processing unit (200) configured to rearrange a plurality of pieces of data input in a first order into a second order, wherein the data rearrangement processing unit (200) includes at least a storage means, the data rearrangement processing unit (200) performs writing of data into the storage means according to a first or second address order, and the data rearrangement processing unit (200) performs data rearrangement processing by performing reading from the storage means according to the second address order for data for which writing is performed in the storage means according to the first address order, and performing reading from the storage means according to the first address order for data for which writing is performed in the storage means according to the second address order.