Digital Filtering Device Using Bit-Reverse Data Ordering
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Solution Overview
Problem
The high cost and power consumption associated with large-capacity storage means required for data rearrangement in FFT/IFFT processing, particularly for large-point FFT, necessitate a reduction in data rearrangement frequency to minimize circuit size and power consumption.
Innovation Solution
A digital filtering device and method that performs FFT and IFFT processes on data in a single sequence, reducing the need for data rearrangement by using a configuration with alternating frequency-domain and time-domain filtering circuits, and implementing data rearrangement through buffer circuits to maintain data in bit-reverse or serial order, thereby minimizing the need for extensive data rearrangement circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data rearrangement is performed frequently in FFT/IFFT processing, then filtering performance is improved, but circuit size and power consumption increase
Solution Approach 1:
The patent applies preliminary action by pre-organizing input data in bit-reverse order before FFT processing begins. This preliminary arrangement eliminates the need for complex data rearrangement circuits during processing, as the data is already in the required sequence for butterfly computations, thereby reducing circuit size while maintaining filtering performance
Solution Approach 2:
The patent extracts the data rearrangement function from the main FFT processing circuit by using separate buffer circuits to maintain data in bit-reverse or serial order. This separation removes the need for complex in-circuit rearrangement logic, reducing the overall circuit size and power consumption while preserving filtering capability
2Productivity
If large-capacity storage means are used for data rearrangement, then FFT processing capability is improved, but power consumption increases
Solution Approach 1:
The patent segments the storage function into separate buffer circuits that handle data in bit-reverse or serial order independently from the main FFT processing unit. This segmentation allows using smaller, more efficient storage elements rather than one large high-power memory, reducing overall power consumption while maintaining FFT processing capability
Solution Approach 2:
The patent changes the data organization parameter from requiring large random-access memory to using buffers that maintain data in specific sequences (bit-reverse or serial order). This parameter change enables the use of smaller, lower-power storage elements that suffice for the required data rearrangement functions
3Measurement precision
If data is rearranged to butterfly computation sequence, then FFT processing accuracy is improved, but processing time increases
Solution Approach 1:
The patent applies preliminary action by pre-arranging data in bit-reverse order in buffer circuits before FFT processing. This preliminary organization eliminates the need for time-consuming data rearrangement during processing, maintaining FFT accuracy while reducing overall processing time
Solution Approach 2:
The patent enables continuous FFT processing by maintaining data in the required bit-reverse order in buffers, allowing the butterfly computation to proceed without interruption for data rearrangement. This continuity preserves processing accuracy while minimizing time loss
Data Source
AI summary
A digital filtering device is provided that makes it possible to reduce the size and power consumption of circuitry for filtering using FFT and IFFT. The digital filtering device includes a first filtering unit for receiving first data in a first sequence, performing a first filtering process including a fast Fourier transformation process and an inverse fast Fourier transformation process on the first data, and outputting second data in the first sequence.