Digital Fine Delay Processing for Continuous Sub-Clock Signal Delay
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Solution Overview
Problem
Conventional methods for delaying analog signals struggle with achieving high-resolution delays less than one clock cycle, often resulting in inaccurate delay control and signal degradation due to the use of analog delay lines, which are not suitable for integrated circuits and are sensitive to temperature variations.
Innovation Solution
A digital fine delay processing method that generates processed digital data with a desired delay by digitally processing source digital data using a convolution function with adjustable coefficients, allowing for a delay resolution greater than one clock cycle and maintaining signal quality by avoiding analog processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an analog delay line is used to provide high-resolution delay control, then delay resolution greater than one clock cycle is achieved, but signal quality degrades and the circuit generates excessive heat making it unsuitable for integrated circuits
Solution Approach 1:
The patent replaces the analog delay line (mechanical/electrical continuous system) with a digital delay line and interpolation circuit. The digital delay line provides coarse delay in integer clock cycles, while the interpolation circuit using hold circuits and DACs provides fine continuous delay adjustment. This substitution eliminates the signal degradation and heat generation issues of analog delay lines while maintaining high resolution delay control capability.
2Measurement precision
If an analog delay line is used to provide high-resolution delay, then delay resolution greater than one clock cycle is achieved, but the circuit becomes difficult to integrate and stable due to temperature sensitivity and part tolerance variability
Solution Approach 1:
The patent replaces temperature-sensitive analog delay line components with digital logic circuits and standard analog components (hold circuits, DACs, low-pass filters) that are well-suited for integrated circuit fabrication. The digital delay line uses flip-flops and multiplexers, while the interpolation circuit uses standard analog building blocks, all of which can be reliably manufactured using standard CMOS or bipolar processes, eliminating temperature sensitivity and part tolerance issues.
3Measurement precision
If digital delay line is used for accurate delay control, then delay accuracy is improved, but only delays that are integer multiples of the clock cycle can be provided, preventing continuous delay control
Solution Approach 1:
The patent segments the delay function into two independent parts: a digital delay line that provides coarse delay in integer clock cycle steps, and an interpolation circuit that provides fine continuous delay adjustment. The digital delay line offers accurate timing control, while the interpolation circuit (using hold circuits, DACs, and low-pass filters) continuously adjusts the delay by interpolating between adjacent digital delay values, achieving both accuracy and continuous adaptability.
Solution Approach 2:
The patent adds a new dimension to the delay control by introducing a continuous analog interpolation layer over the discrete digital delay stages. Instead of simply extending the digital delay line, the invention uses the output of the digital delay line to control variable delay elements in the analog domain, creating a two-stage control mechanism that combines discrete precision with continuous flexibility.
Data Source
AI summary
Digital fine delay processing provides an accurate and continuous delay for an analog signal generated from source digital data. A digital processor generates processed digital data corresponding to a delayed analog signal having a desired delay relative to the analog signal represented by the source digital data. The processed digital data is directly derived from the source digital data by digital processing, and both digital data are processed by a reference clock, or by the same phase and cycle of the reference clock. The processed digital data is converted into a the delayed analog signal. Modifying coefficients in a convolution function performed by the digital processor changes the desired delay so that the delay is accurately controlled and is continuous. Since the entire process is digital, degradation of the delayed analog signal is minimal.