Digital Focal Plane Readout Using 2D ADC Arrays for High Frame Rates
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Solution Overview
Problem
Conventional focal plane arrays (FPAs) face limitations in achieving high frame rates, wide dynamic range, and low power consumption due to capacitor size limitations and electronics noise, making them unsuitable for demanding imaging applications like long-wave infrared imaging.
Innovation Solution
A two-dimensional array of self-contained analog-to-digital converters (ADCs) that convert current mode signals to digital signals within the array, eliminating the need for large charge storage capacitors and highly linear analog electronics, and allowing for digital signal processing, such as filtering and data compression, while operating independently of external signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional analog readout designs are used to achieve high frame rates, then frame rate is improved, but capacitor size must be increased which leads to larger device area and higher power consumption
Solution Approach 1:
The patent divides the focal plane array into multiple independent readout channels, each with its own small capacitor and ADC. This segmentation allows each channel to operate independently with reduced capacitor size while maintaining high frame rates through parallel processing of multiple channels.
Solution Approach 2:
The patent replaces the traditional mechanical/analog readout system with a digital system. Each pixel channel includes an ADC that converts analog signals to digital signals on-chip, eliminating the need for large analog capacitors and external analog processing, thereby reducing capacitor size and power consumption while enabling high frame rates.
2Reliability
If conventional analog readout designs are used to achieve wide dynamic range, then dynamic range is improved, but electronics noise increases which limits data transmission quality
Solution Approach 1:
The patent replaces analog signal processing with digital signal processing by integrating ADCs at each pixel channel. This substitution converts analog signals to digital signals on-chip, eliminating the propagation of analog noise through the readout circuitry and enabling wide dynamic range with low noise through digital processing techniques.
Solution Approach 2:
The patent introduces digital signal processing as an intermediary between the sensor pixels and the output. The ADCs and on-chip digital processing circuits act as intermediaries that convert and process signals in the digital domain, where noise can be more effectively managed and dynamic range can be extended through digital techniques.
3Manufacturing precision
If conventional analog readout designs are used to achieve high spatial resolution, then spatial resolution is improved, but device complexity increases leading to larger and more complex sensor systems
Solution Approach 1:
The patent merges multiple functions (ADC, digital signal processing, data formatting) into integrated on-chip circuits at each pixel channel. This consolidation eliminates the need for separate external processing components, reducing overall device complexity while maintaining high spatial resolution through precise on-chip signal conversion and processing.
Solution Approach 2:
The patent creates universal on-chip readout circuits that perform multiple functions (signal conversion, processing, and output) within each pixel channel. This multi-functionality reduces the need for specialized external components and simplifies the overall sensor system architecture while supporting high spatial resolution imaging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power dissipation and noise, enabling high-resolution imaging with lower power consumption and smaller feature sizes, allowing for more compact and efficient digital focal plane arrays that can handle high frame rates and wide dynamic ranges.
Implementation Method 1
a capacitor may be employed to integrate charge from the current mode signal and the capacitor and ADC architecture may be selected to determine the least significant bit of each of the ADCs
Data Source
AI summary
Autonomously operating analog to digital converters are formed into a two dimensional array. The array may incorporate digital signal processing functionality. Such an array is particularly well-suited for operation as a readout integrated circuit and in combination with a sensor array, forms a digital focal plane array.