Digital Frequency Channelizer Using Cascaded Filter-Decimation-Tuning Stages

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Solution Overview

Problem

The Fast Fourier Transform (FFT) algorithm is limited in producing only one set of equally-split output channels for a given length, restricting its ability to simultaneously generate multiple sets of filtered channelized outputs over varying bandwidths.

Innovation Solution

A digital frequency channelizer architecture that employs successive stages of filtering, decimation, and tuning to generate multiple sets of equally-split output channels, increasing the number of channels by a factor of 2 at each stage, suitable for hardware implementation in FPGAs and software, and utilizing FIR filters and decimators to achieve efficient signal processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If FFT algorithm is used with a given length, then one set of equally-split output channels is produced, but the ability to simultaneously generate multiple sets of filtered channelized outputs over varying bandwidths is restricted

Engineering Contradiction:
Improveability to generate multiple sets of filtered channelized outputs over varying bandwidthsVSAvoidarchitecture complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the spectrum into multiple frequency bands using a bank of filters, where each filter processes a specific frequency range. This segmentation allows simultaneous generation of multiple channelized outputs with different bandwidths, resolving the limitation of FFT producing only one set of equally-split channels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The filter bank architecture allows dynamic adjustment of filter bandwidths and center frequencies, enabling the system to adaptively generate multiple sets of channelized outputs with varying bandwidths. This dynamic capability contrasts with the fixed-length FFT approach.

Inventive Principle:
Principle #15Dynamics

2Productivity

If multiple sets of equally-split output channels are produced simultaneously, then the number of channels increases by a factor of 2 for each additional stage, but resource requirements increase

Engineering Contradiction:
Improvenumber of channels produced simultaneouslyVSAvoidlogic resources and memory resources
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The signal processing task is segmented into multiple stages, where each stage processes a subset of frequency bands. This segmentation allows the system to produce multiple channel sets simultaneously while distributing computational load across stages, reducing peak resource requirements compared to processing all channels in a single FFT operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each filter in the bank processes only the specific frequency band it is designed for, performing partial action on the overall signal. This approach produces the necessary channelized outputs without the excessive computation required by a full-length FFT, thereby reducing logic and memory resource requirements.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8452826B2Digital frequency channelizer
Publication Date: 2013.05.28 RAYTHEON APPLIED SIGNAL TECHNOLOGY INC
  • US8452826B2 patent drawing
  • US8452826B2 patent drawing
  • US8452826B2 patent drawing

AI summary

A method and apparatus provide digital frequency channelization of a digitally sampled input stream having a first bandwidth. The method and apparatus are implementable in software, firmware or hardware and convert a first set of real samples from the input stream into a first plurality of complex samples with a first functional block performing filtering, decimation and tuning functions, convert the first plurality of complex samples into a first pair of consecutive USB and a first pair of consecutive LSB complex samples with a second functional block performing filtering, decimation and tuning functions, and convert the first pair of consecutive USB and the first pair of consecutive LSB complex samples into a two pairs of complex USB and LSB complex samples with a pair of third functional blocks performing filtering, decimation and tuning functions, and apply the two pairs of complex USB and LSB complex samples to a string of n pairs (for n greater than or equal to one) third functional blocks each performing filtering, decimation and tuning functions.