Digital Frequency Synthesizer Using Coarse-Fine Delay Tuning

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Solution Overview

Problem

Conventional frequency synthesizers face limitations in achieving a wide dynamic range and high frequency variations while maintaining low power consumption and area efficiency, particularly in advanced communication systems like LTE with carrier aggregation, due to trade-offs between static and dynamic frequency tuning, maximum modulation speed, phase noise, and cross-coupling between parallel paths.

Innovation Solution

A circuit comprising a delay generator and a delay element that provide a synthesized signal with a selectable frequency by combining coarse and fine delays, allowing for high dynamic range and accurate frequency variations, implemented using a multi-modulus divider and digitally-controlled delay, which operates on a clock signal to generate signal edges at arbitrary times with high time resolution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional frequency synthesizers use parallel paths for frequency tuning, then frequency range is improved, but cross-coupling between paths increases causing interference

Engineering Contradiction:
Improvefrequency rangeVSAvoidcross-coupling interference
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The frequency tuning range is divided into two independent segments: a coarse tuning range achieved by varying the division ratio of a single divider, and a fine tuning range achieved by digitally controlling the delay element. This segmentation allows the synthesizer to achieve wide frequency range without requiring multiple parallel analog paths that would cause cross-coupling interference.

Inventive Principle:
Principle #1Segmentation

2Speed

If analog oscillator signals are used for fast frequency variation, then modulation speed is improved, but phase noise and power consumption increase

Engineering Contradiction:
Improvemodulation speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent replaces the mechanical/analog oscillator system with a purely digital implementation. The frequency synthesizer uses digital logic elements (divider, delay element controlled by digital signals) to generate frequency variations, eliminating the need for analog oscillators. This substitution achieves fast modulation speed through digital switching while significantly reducing power consumption and avoiding phase noise issues associated with analog oscillators.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If digitally-controlled oscillators are used for frequency synthesis, then frequency accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvefrequency accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent employs a single divider that can perform multiple functions: it provides both the coarse frequency tuning through variable division ratio and works in conjunction with the delay element for fine tuning. This multi-functional approach eliminates the need for separate dedicated circuits for each tuning function, thereby reducing overall device complexity while maintaining high frequency accuracy through digital control.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9281811B2Circuit, a method and a synthesizer for generating a synthesized signal with a selectable frequency
Publication Date: 2016.03.08 INTEL CORP
  • US9281811B2 patent drawing
  • US9281811B2 patent drawing
  • US9281811B2 patent drawing

AI summary

A circuit for generating a oscillating with a selectable frequency, comprises a delay generator configured to identify a first time instant, the first time instant being delayed with respect to a signal edge of a clock signal oscillating with a predetermined clock frequency. A delay element is configured to provide a signal edge, the signal edge being delayed with respect to the first time instant such that the signal edge is provided at a second time instant corresponding to a signal edge of the synthesized signal.