Digital Frequency Discriminator Feedback for Clock Phase Noise
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Solution Overview
Problem
As electronic devices require higher data rates for increasingly data-intensive software applications, supporting wireless communications at frequencies greater than 100 GHz poses challenges due to difficulties in providing low phase noise clocking for wireless circuitry, especially in minimizing space and power consumption.
Innovation Solution
Incorporating a digital frequency discriminator (DFD) in the clocking circuitry with a signal source and a loop path, which includes a digital mixer, digital delay circuitry, and a digital phase shifter to generate a control signal that mitigates phase noise, while minimizing space and power consumption compared to analog frequency discriminators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wireless communications operate at higher frequencies to support higher data rates, then data rate capability is improved, but phase noise in clock signals increases
Solution Approach 1:
The patent implements a feedback mechanism where the digital frequency discriminator continuously monitors the clock signal phase noise and generates control signals that are fed back to the signal source. This closed-loop feedback system dynamically adjusts the clock signal to mitigate phase noise, enabling high-frequency wireless communications with controlled phase noise levels.
Solution Approach 2:
The patent replaces traditional analog frequency discriminators with a digital implementation. The digital frequency discriminator uses digital signal processing techniques including digital mixing, digital delay elements, and digital phase shifters to measure and control phase noise, thereby reducing hardware complexity and power consumption while maintaining effective phase noise mitigation at high frequencies.
2Reliability
If analog frequency discriminators are used to minimize phase noise, then phase noise control is improved, but space and power consumption increase
Solution Approach 1:
The patent substitutes analog frequency discriminator circuitry with a digital frequency discriminator implemented using digital logic elements. This includes digital mixers, digital delay elements, and digital phase shifters that operate in the digital domain. The digital implementation reduces power consumption and hardware area while maintaining the phase noise measurement and control functionality through software-configurable digital signal processing.
Solution Approach 2:
The patent changes the operating domain from analog to digital, fundamentally altering how phase noise is measured and controlled. By using digital sampling, digital mixing, and digital signal processing, the system achieves the same phase noise mitigation function with reduced power consumption and improved integrability into modern wireless communication devices.
Data Source
AI summary
An electronic device may include wireless circuitry that conveys wireless signals and that is clocked using clocking circuitry. The clocking circuitry may include a signal source that generates a clock signal and a loop path coupled between the input and the output of the signal source. A digital frequency discriminator (DFD) may be disposed on the loop path. The DFD may include a digital delay and digital phase shifter coupled between an input converter and a digital mixer. The DFD may receive the clock signal and may generate a control signal indicative of phase noise of the clock signal. The DFD may feed the control signal back into the input of the signal source to mitigate the phase noise. The DFD may minimize phase noise of the signal source while minimizing space and power consumption on the device relative to analog frequency discriminators.