Digital Frequency Divider for Programmable I/Q Clock Synthesis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional frequency synthesizers face performance and cost efficiency degradation at low reference frequencies, requiring complex modifications to generate programmable clock signals over a wide bandwidth, especially for in-phase and quadrature-phase (I/Q) outputs, due to issues with phase-locked loops and increased power consumption.
Innovation Solution
A programmable frequency synthesizer design that uses a post-scaler instead of a prescaler, with a digital frequency divider comprising two sub-dividing stages and a duty cycle equalizer to generate I/Q clock signals without frequency doubling, allowing for efficient operation across a wide range of frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop is used to generate clock signals at low reference frequencies, then frequency stability is maintained, but design complexity and cost efficiency are degraded
Solution Approach 1:
The patent replaces the conventional phase-locked loop (analog/mixed-signal system) with a digital frequency synthesizer architecture. The digital frequency divider and counter-based frequency generation eliminate the need for phase detectors, charge pumps, and analog loop filters, substituting complex analog circuitry with simpler digital logic while maintaining frequency stability through programmable division ratios.
Solution Approach 2:
The invention changes the operating parameters of the frequency synthesizer by using a high reference frequency (e.g., 19.2 MHz or 24 MHz) combined with large integer division ratios in the digital frequency divider. This parameter change allows the system to generate low output frequencies without requiring the phase-locked loop to operate at low frequencies, thereby avoiding the associated complexity and cost issues.
2Speed
If a phase-locked loop operates at low reference frequencies, then low output frequencies are achieved, but charge-pump current and loop filter component size increase
Solution Approach 1:
The patent eliminates the charge pump and analog loop filter by replacing the phase-locked loop with a digital frequency synthesizer. The digital frequency divider and counter-based architecture require no external passive components, completely removing the loop filter capacitor and associated large component size issues while achieving low output frequencies through high-ratio digital division.
3Adaptability or versatility
If frequency doubling is used to generate quadrature-phase signals, then I/Q clock outputs are achieved, but design complexity and power consumption increase
Solution Approach 1:
The patent segments the frequency division process into multiple stages: a digital frequency divider generates the base frequency, and separate counter-based circuits generate the in-phase and quadrature-phase signals. This segmentation avoids the need for frequency doubling while providing I/Q outputs, reducing design complexity by eliminating the need for complex quadrature generation circuitry.
4Reliability
If a narrow loop bandwidth is used to achieve low cutoff frequency, then frequency stability is improved, but settling time increases
Solution Approach 1:
The patent replaces the phase-locked loop with a digital frequency synthesizer that uses a phase accumulator and digital frequency divider. This architecture provides instantaneous frequency switching capability, eliminating the settling time issue inherent in analog phase-locked loops with narrow bandwidths. The digital system can change output frequency immediately by updating the division ratio without requiring the loop to settle.
Data Source
AI summary
Various embodiments of the present invention relate to systems, devices and method of frequency synthesis that generate in-phase and quadrature-phase clock signals at a programmable frequency. The generated frequency, which can range from a fraction to multiples of the input reference frequency, is generated by dividers following a phase-locked loop, thus avoiding the use of a low input reference frequency as well as frequency doubling.