Digital Frequency Doubler With Adjustable Duty Cycle Control
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Solution Overview
Problem
Conventional frequency doubler circuits are not power efficient and lack digital circuit nature, limiting their ability to control duty cycle beyond 50% outputs, which is not suitable for all applications.
Innovation Solution
A frequency doubler circuit comprising a multiplexer, digitally controlled delay circuit, divide-by-two circuit, duty cycle detector, and controller, which allows for digital control of duty cycle by selecting phases of the input clock, delaying signals, and adjusting propagation delays to achieve a target duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an analog frequency doubler circuit is used to generate 50% duty cycle output, then the duty cycle precision is improved, but the power consumption increases and the circuit complexity increases
Solution Approach 1:
The patent replaces the analog frequency doubler circuit with a digital frequency doubler circuit. The digital circuit uses digital logic elements (D-flip flops, multiplexers, XOR gates) instead of analog components (current generators, capacitors). This substitution maintains the 50% duty cycle precision while significantly reducing power consumption and simplifying the circuit structure.
Solution Approach 2:
The patent introduces duty cycle control by changing the phase difference parameter between the two phases of the input clock. By controlling the phase difference (e.g., 0°, 90°, 180°), the circuit can generate output clocks with different duty cycles (50%, 25%, 75%), thereby extending the functionality beyond fixed 50% duty cycle while maintaining digital efficiency.
2Measurement precision
If an analog frequency doubler circuit is used to generate 50% duty cycle output, then the duty cycle precision is improved, but the device complexity increases
Solution Approach 1:
The patent replaces the analog frequency doubler circuit with a digital frequency doubler circuit. The digital circuit uses digital logic elements (D-flip flops, multiplexers, XOR gates) instead of analog components (current generators, capacitors). This substitution maintains the 50% duty cycle precision while significantly simplifying the circuit structure.
Solution Approach 2:
The patent designs a universal digital frequency doubler circuit that can generate multiple duty cycles (50%, 25%, 75%, etc.) by controlling the phase difference between input clock phases. This multi-functional design eliminates the need for separate circuits for different duty cycles, thereby reducing overall device complexity while maintaining precision.
3Device complexity
If a fixed 50% duty cycle frequency doubler is used, then the circuit simplicity is improved, but the adaptability decreases
Solution Approach 1:
The patent introduces dynamic control to the frequency doubler circuit by enabling adjustment of the phase difference between the two phases of the input clock. This dynamic adjustment capability allows the circuit to adapt to different duty cycle requirements (50%, 25%, 75%, etc.) while maintaining a relatively simple digital circuit structure, thereby achieving both simplicity and adaptability.
Solution Approach 2:
The patent achieves duty cycle adaptability by changing the phase difference parameter between input clock phases. By controlling this parameter (e.g., 0°, 90°, 180°), the circuit can generate different duty cycles without requiring complex reconfiguration, thus maintaining circuit simplicity while enhancing adaptability.
4Adaptability or versatility
If a digital frequency doubler with phase control is used, then the duty cycle versatility is improved, but the device complexity increases
Solution Approach 1:
The patent designs a universal digital frequency doubler circuit that integrates multiple duty cycle generation capabilities (50%, 25%, 75%, etc.) into a single circuit structure. By using common digital logic elements (D-flip flops, multiplexers, XOR gates) with controllable phase differences, the circuit achieves multi-functionality without proportionally increasing complexity.
Solution Approach 2:
The patent achieves duty cycle versatility through parameter control (phase difference adjustment) rather than structural changes. This approach allows the circuit to generate multiple duty cycles by simply changing control parameters, thereby achieving versatility while maintaining relatively simple circuit structure.
Data Source
AI summary
A frequency doubler includes a multiplexer, a digitally controlled delay circuit, a divide-by-two circuit, a duty cycle detector, and a controller. The multiplexer receives a first clock and output a second clock in accordance with a third clock, in which the first clock has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase. The digitally controlled delay circuit receives the second clock and outputs a fourth clock in accordance with a digital word. The divide-by-two circuit receives the fourth clock and outputs the third clock. The duty cycle detector receives the second clock and outputs a logical signal in accordance with a comparison of a duty cycle of the second clock with a target duty cycle value. The controller outputs the digital word in accordance with the logical signal.