Digital Frequency Locked Loop Supply Voltage Control
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Solution Overview
Problem
Existing digital frequency locked loops require a voltage margin to account for dynamic fluctuations, leading to increased power consumption and potential system failures due to reduced supply voltage.
Innovation Solution
A digital frequency locked loop system that uses the supply voltage as a control input to generate a clock signal, maintaining the supply voltage within an acceptable range while adjusting the clock frequency, using a digital voltage controlled oscillator and feedback control means to ensure stability and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage margin is added to account for dynamic fluctuations, then system reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements a feedback mechanism where the supply voltage is continuously monitored and fed back to the DVCO. The feedback control means adjusts the supply voltage in real-time based on the actual voltage level and frequency requirements, eliminating the need for static voltage margin while maintaining system reliability through dynamic adaptation.
Solution Approach 2:
The system transitions from a static voltage margin approach to a dynamic voltage control approach. The supply voltage is continuously adjusted based on real-time conditions, allowing the system to operate at optimal voltage levels without requiring excessive margin, thereby reducing power consumption while maintaining reliability.
2Use of energy by moving object
If supply voltage is reduced to lower power consumption, then power consumption decreases, but system reliability deteriorates due to potential failures
Solution Approach 1:
The feedback control means continuously monitors the supply voltage and frequency, and dynamically adjusts the voltage to maintain it within acceptable ranges. This real-time adjustment capability allows the system to operate at lower voltages without compromising reliability, as the feedback mechanism ensures voltage remains sufficient for proper operation.
Solution Approach 2:
The system uses its own supply voltage as a control input to the DVCO, creating a self-regulating mechanism. The voltage-controlled oscillator naturally adapts its frequency output based on the supply voltage level, and the feedback loop ensures the voltage remains within operational limits, eliminating the need for external voltage margin while maintaining reliability.
3Speed
If frequency is adjusted by varying supply voltage, then frequency control is achieved, but voltage must be reduced outside acceptable range causing system failures
Solution Approach 1:
The feedback control means monitors both frequency and supply voltage, and dynamically adjusts the voltage to maintain it within acceptable ranges while achieving the desired frequency. This coordinated control prevents voltage from dropping below operational thresholds, ensuring system reliability while enabling frequency adjustment.
Solution Approach 2:
The system changes multiple parameters simultaneously - both supply voltage and DVCO control input - to achieve frequency adjustment while maintaining voltage within acceptable ranges. By using the supply voltage itself as a control input and adjusting it in coordination with the frequency requirements, the system can vary frequency without causing voltage to drop outside acceptable ranges.
Data Source
AI summary
Integrated circuit and method for generating a clock signal, the integrated circuit comprising (i) a frequency locked loop comprising a voltage controlled oscillator configured to receive a control input and to generate a clock signal determined by the control input; and (ii) a microprocessor configured to be powered by a supply voltage and to receive the clock signal generated by the voltage controlled oscillator. The integrated circuit is configured to use the supply voltage as the control input, such that the clock signal is determined by the supply voltage.