Digital Count-Locked Frequency Synthesizer Without Loop Filters
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing frequency synthesizers face challenges with stability issues due to large area occupation by loop filters and sensitivity to processes in analog blocks, particularly in high-speed and wireless circuits, and often suffer from instability in 2nd or higher order closed loops.
Innovation Solution
An all-digital count lock loop (CLL) frequency synthesizer with a feed forward approach, utilizing a divider controller and a digitally controlled oscillator to generate output frequencies by dividing a reference oscillator signal by a multiplier value, and incorporating a feedback loop for error reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a phase-locked loop (PLL) circuit is used for frequency synthesis, then multiple clock signals can be generated from a single reference signal, but the loop filter occupies a relatively large area and stability issues arise in 2nd or higher order closed loops
Solution Approach 1:
The patent extracts and removes the loop filter component from the frequency synthesis system, transitioning from a PLL-based analog approach to a counter-based digital approach. This eliminates the need for a physical loop filter while maintaining frequency synthesis functionality through digital counting and division mechanisms.
Solution Approach 2:
The patent replaces the analog PLL mechanism with a digital counter-based system. The continuous analog feedback loop is substituted with discrete digital counting operations, eliminating the need for analog components like loop filters and replacing them with digital logic elements such as counters and dividers.
2Productivity
If analog blocks such as voltage controlled oscillators (VCO) are used in frequency synthesizer circuits, then frequency generation is achieved, but the circuits become sensitive to particular processes
Solution Approach 1:
The patent replaces analog VCO blocks with digital oscillators that generate clock signals through digital logic circuits. This substitution eliminates the process sensitivity inherent in analog components while maintaining frequency generation capability through digitally controlled oscillation mechanisms.
Solution Approach 2:
The patent changes the operational parameters from analog voltage control to digital control signals. Frequency generation is achieved through digital division ratios and counter values rather than analog voltage adjustments, making the system less sensitive to process variations and more predictable across different manufacturing conditions.
3Measurement precision
If a feedback loop is implemented for error reduction in frequency synthesis, then output frequency accuracy is improved, but the system complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the counter output is compared with a reference value, and the difference (error signal) is used to adjust the oscillation frequency. This digital feedback loop provides frequency accuracy while using simple digital comparison and adjustment logic rather than complex analog control circuits.
Data Source
AI summary
A frequency synthesizer comprising a reference oscillator configured to generate a first clock signal with a reference frequency and a divider controller configured to receive the first clock signal, a second clock signal, and a multiplier value. The divider controller is configured to obtain a ratio of a frequency of the first clock signal to a frequency of the second clock signal and divide the resulting ratio by the multiplier value to obtain controller output value. A divider is configured to receive the first clock signal and controller output value and output an output clock signal with a frequency equal to the frequency of the first clock signal divided by the controller output value.